From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
peter.maydell@linaro.org, richard.henderson@linaro.org,
"Víctor Colombo" <victor.colombo@eldorado.org.br>
Subject: [PULL 30/30] target/ppc: Change MSR_* to follow POWER ISA numbering convention
Date: Thu, 5 May 2022 15:49:38 -0300 [thread overview]
Message-ID: <20220505184938.351866-31-danielhb413@gmail.com> (raw)
In-Reply-To: <20220505184938.351866-1-danielhb413@gmail.com>
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Today we have the issue where MSR_* values are the 'inverted order'
bit numbers from what the ISA specifies. e.g. MSR_LE is bit 63 but
is defined as 0 in QEMU.
Add a macro to be used to convert from QEMU order to ISA order.
This solution requires less changes than to use the already defined
PPC_BIT macro, which would turn MSR_* in masks instead of the numbers
itself.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-23-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.h | 87 ++++++++++++++++++++++++------------------------
1 file changed, 44 insertions(+), 43 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4577cfcc23..48596cfb25 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -38,6 +38,7 @@
#define PPC_ELF_MACHINE EM_PPC
#endif
+#define PPC_BIT_NR(bit) (63 - (bit))
#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
#define PPC_BIT32(bit) (0x80000000 >> (bit))
#define PPC_BIT8(bit) (0x80 >> (bit))
@@ -310,49 +311,49 @@ typedef enum {
/*****************************************************************************/
/* Machine state register bits definition */
-#define MSR_SF 63 /* Sixty-four-bit mode hflags */
-#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
-#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
-#define MSR_HV 60 /* hypervisor state hflags */
-#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
-#define MSR_TS1 33
-#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
-#define MSR_CM 31 /* Computation mode for BookE hflags */
-#define MSR_ICM 30 /* Interrupt computation mode for BookE */
-#define MSR_GS 28 /* guest state for BookE */
-#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
-#define MSR_VR 25 /* altivec available x hflags */
-#define MSR_SPE 25 /* SPE enable for BookE x hflags */
-#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
-#define MSR_S 22 /* Secure state */
-#define MSR_KEY 19 /* key bit on 603e */
-#define MSR_POW 18 /* Power management */
-#define MSR_WE 18 /* Wait State Enable on 405 */
-#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
-#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
-#define MSR_ILE 16 /* Interrupt little-endian mode */
-#define MSR_EE 15 /* External interrupt enable */
-#define MSR_PR 14 /* Problem state hflags */
-#define MSR_FP 13 /* Floating point available hflags */
-#define MSR_ME 12 /* Machine check interrupt enable */
-#define MSR_FE0 11 /* Floating point exception mode 0 */
-#define MSR_SE 10 /* Single-step trace enable x hflags */
-#define MSR_DWE 10 /* Debug wait enable on 405 x */
-#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
-#define MSR_BE 9 /* Branch trace enable x hflags */
-#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
-#define MSR_FE1 8 /* Floating point exception mode 1 */
-#define MSR_AL 7 /* AL bit on POWER */
-#define MSR_EP 6 /* Exception prefix on 601 */
-#define MSR_IR 5 /* Instruction relocate */
-#define MSR_DR 4 /* Data relocate */
-#define MSR_IS 5 /* Instruction address space (BookE) */
-#define MSR_DS 4 /* Data address space (BookE) */
-#define MSR_PE 3 /* Protection enable on 403 */
-#define MSR_PX 2 /* Protection exclusive on 403 x */
-#define MSR_PMM 2 /* Performance monitor mark on POWER x */
-#define MSR_RI 1 /* Recoverable interrupt 1 */
-#define MSR_LE 0 /* Little-endian mode 1 hflags */
+#define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
+#define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
+#define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
+#define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */
+#define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */
+#define MSR_TS1 PPC_BIT_NR(30)
+#define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
+#define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
+#define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
+#define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
+#define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
+#define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
+#define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
+#define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
+#define MSR_S PPC_BIT_NR(41) /* Secure state */
+#define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
+#define MSR_POW PPC_BIT_NR(45) /* Power management */
+#define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
+#define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
+#define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
+#define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
+#define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
+#define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
+#define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
+#define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
+#define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
+#define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
+#define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
+#define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
+#define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
+#define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
+#define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
+#define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
+#define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
+#define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
+#define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
+#define MSR_DR PPC_BIT_NR(59) /* Data relocate */
+#define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
+#define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
+#define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
+#define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
+#define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
+#define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
FIELD(MSR, SF, MSR_SF, 1)
FIELD(MSR, TAG, MSR_TAG, 1)
--
2.32.0
next prev parent reply other threads:[~2022-05-05 20:08 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 18:49 [PULL 00/30] ppc queue Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 01/30] target/ppc: initialize 'val' union in kvm_get_one_spr() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 02/30] target/ppc: init 'lpcr' in kvmppc_enable_cap_large_decr() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 03/30] target/ppc: init 'sregs' in kvmppc_put_books_sregs() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 04/30] target/ppc: init 'rmmu_info' in kvm_get_radix_page_info() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 05/30] target/ppc: Fix BookE debug interrupt generation Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 06/30] vhost-user: Use correct macro name TARGET_PPC64 Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 07/30] ppc/xive: Always recompute the PIPR when pushing an OS context Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 08/30] ppc/xive: Update the state of the External interrupt signal Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 09/30] target/ppc: Remove fpscr_* macros from cpu.h Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 10/30] target/ppc: Remove unused msr_* macros Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 11/30] target/ppc: Remove msr_pr macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 12/30] target/ppc: Remove msr_le macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 13/30] target/ppc: Remove msr_ds macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 14/30] target/ppc: Remove msr_ile macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 15/30] target/ppc: Remove msr_ee macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 16/30] target/ppc: Remove msr_ce macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 17/30] target/ppc: Remove msr_pow macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 18/30] target/ppc: Remove msr_me macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 19/30] target/ppc: Remove msr_gs macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 20/30] target/ppc: Remove msr_fp macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 21/30] target/ppc: Remove msr_cm macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 22/30] target/ppc: Remove msr_ir macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 23/30] target/ppc: Remove msr_dr macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 24/30] target/ppc: Remove msr_ep macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 25/30] target/ppc: Remove msr_fe0 and msr_fe1 macros Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 26/30] target/ppc: Remove msr_ts macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 27/30] target/ppc: Remove msr_hv macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 28/30] target/ppc: Remove msr_de macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 29/30] target/ppc: Add unused msr bits FIELDs Daniel Henrique Barboza
2022-05-05 18:49 ` Daniel Henrique Barboza [this message]
2022-05-06 4:17 ` [PULL 00/30] ppc queue Richard Henderson
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