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From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: Kirill Marinushkin <kmarinushkin@birdec.com>
Cc: oder_chiou@realtek.com, steven.eckhoff.opensource@gmail.com,
	alexandre.belloni@bootlin.com, lars@metafoo.de,
	kuninori.morimoto.gx@renesas.com,
	chrome-platform@lists.linux.dev, patches@opensource.cirrus.com,
	lgirdwood@gmail.com, jiaxin.yu@mediatek.com, tzungbi@google.com,
	broonie@kernel.org, srinivas.kandagatla@linaro.org,
	matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org,
	codrin.ciubotariu@microchip.com, alsa-devel@alsa-project.org,
	bleung@chromium.org, cychiang@chromium.org
Subject: Re: [PATCH 01/38] ASoC: soc-component: Add comment for the endianness flag
Date: Tue, 10 May 2022 08:53:23 +0000	[thread overview]
Message-ID: <20220510085323.GA38351@ediswmail.ad.cirrus.com> (raw)
In-Reply-To: <901cb995-4a82-741e-00ea-a1c0b22ae749@birdec.com>

On Mon, May 09, 2022 at 09:22:42PM +0200, Kirill Marinushkin wrote:
> On 5/9/22 10:37 AM, Charles Keepax wrote:
> >On Sun, May 08, 2022 at 10:34:12PM +0200, Kirill Marinushkin wrote:
> >This sounds like an error on the CPU side of the DAI link rather
> >than the CODEC side of the DAI link. The formats that will be
> >supported on the link are the union of the CPU and CODEC supported
> >formats, ie. a format must be supported on both for the DAI to
> >support it.
> 
> Yes, agree, both sides of the DAI link should provide only
> endianness they support.
> 
> This works currently, but, from my understending, it will break,
> after we set `endianness = 1`.

It will break if the CPU side claims it supports endians which it
doesn't which I believe is what you have in your system.

> As soon as we start setting `endianness = 1`, the function
> `convert_endianness_formats()` will extend LE to (LE | BE), right?

Correct.

> If so, setting `endianness = 1` is the source of an error, right?

No, potentially it exposes an error but it is not the source of the
error. Endian should have no meaning once you cross an I2S bus.

> >If this is not the case then
> >the host I2S controller is claiming to support an endian it does
> >not, and the problem should be fixed on that side by removing the
> >supported endian.
> 
> I think we have a misundersanding of my example.
> 
> In my example, i don't mean, that my CPU part of the DAI link is broken.

Why are you sure the CPU part of the DAI link isn't broken? I2S
defines the order bits should be sent out on the bus, this means if
the CPU side recieves big endian or little endian data it doesn't
matter, the actual bus signals should be identical in both cases.
If only one endian works the actual signals on the bus must have
been different depending on which endian you played in which case
the host side doesn't match the I2S specification.

My point is that what you are seeing is exactly what you get if
your CPU DAI claimed to support both big and little endian but
just puts that data directly out on the bus, rather than adapting
to the endian of data it receives.

And to be fair this is exactly what I am trying to tackle with this
series. The fact we have so many CODECs that are incorrectly not
specifying the endianness flag means that it is very easy for the
host side guys to do testing and not realise that the CODEC is the
one limiting the supported endians on the DAI link and thus miss
they have claimed to support endians they don't.

I believe you are right that there is a reasonable chance will see
some breakage after these patches, but that breakage should be
exposing host side bugs which we need to fix anyway.

> What i tried to demonstrate - is that if i set the unsupported
> endianness, i wouldn't expect that "the CODEC probably can care
> about the endian", as the message in [PATCH 00/38] suggests.

That comment in my original post was in respect to CODECs that
recieve/transmit audio directly over a SPI bus rather than a
normal audio bus. The is no standard governing how audio data is
transmitted over the SPI bus, thus endian could be important,
although I need to do some more work to analyse how people are
using these links. Often they are implemented effectively as a
CPU side DAI anyway.

Thanks,
Charles

WARNING: multiple messages have this Message-ID (diff)
From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: Kirill Marinushkin <kmarinushkin@birdec.com>
Cc: <broonie@kernel.org>, <lgirdwood@gmail.com>,
	<codrin.ciubotariu@microchip.com>, <lars@metafoo.de>,
	<cychiang@chromium.org>, <tzungbi@google.com>,
	<bleung@chromium.org>, <matthias.bgg@gmail.com>,
	<oder_chiou@realtek.com>, <steven.eckhoff.opensource@gmail.com>,
	<srinivas.kandagatla@linaro.org>, <alexandre.belloni@bootlin.com>,
	<kuninori.morimoto.gx@renesas.com>, <jiaxin.yu@mediatek.com>,
	<alsa-devel@alsa-project.org>, <chrome-platform@lists.linux.dev>,
	<linux-mediatek@lists.infradead.org>,
	<patches@opensource.cirrus.com>
Subject: Re: [PATCH 01/38] ASoC: soc-component: Add comment for the endianness flag
Date: Tue, 10 May 2022 08:53:23 +0000	[thread overview]
Message-ID: <20220510085323.GA38351@ediswmail.ad.cirrus.com> (raw)
In-Reply-To: <901cb995-4a82-741e-00ea-a1c0b22ae749@birdec.com>

On Mon, May 09, 2022 at 09:22:42PM +0200, Kirill Marinushkin wrote:
> On 5/9/22 10:37 AM, Charles Keepax wrote:
> >On Sun, May 08, 2022 at 10:34:12PM +0200, Kirill Marinushkin wrote:
> >This sounds like an error on the CPU side of the DAI link rather
> >than the CODEC side of the DAI link. The formats that will be
> >supported on the link are the union of the CPU and CODEC supported
> >formats, ie. a format must be supported on both for the DAI to
> >support it.
> 
> Yes, agree, both sides of the DAI link should provide only
> endianness they support.
> 
> This works currently, but, from my understending, it will break,
> after we set `endianness = 1`.

It will break if the CPU side claims it supports endians which it
doesn't which I believe is what you have in your system.

> As soon as we start setting `endianness = 1`, the function
> `convert_endianness_formats()` will extend LE to (LE | BE), right?

Correct.

> If so, setting `endianness = 1` is the source of an error, right?

No, potentially it exposes an error but it is not the source of the
error. Endian should have no meaning once you cross an I2S bus.

> >If this is not the case then
> >the host I2S controller is claiming to support an endian it does
> >not, and the problem should be fixed on that side by removing the
> >supported endian.
> 
> I think we have a misundersanding of my example.
> 
> In my example, i don't mean, that my CPU part of the DAI link is broken.

Why are you sure the CPU part of the DAI link isn't broken? I2S
defines the order bits should be sent out on the bus, this means if
the CPU side recieves big endian or little endian data it doesn't
matter, the actual bus signals should be identical in both cases.
If only one endian works the actual signals on the bus must have
been different depending on which endian you played in which case
the host side doesn't match the I2S specification.

My point is that what you are seeing is exactly what you get if
your CPU DAI claimed to support both big and little endian but
just puts that data directly out on the bus, rather than adapting
to the endian of data it receives.

And to be fair this is exactly what I am trying to tackle with this
series. The fact we have so many CODECs that are incorrectly not
specifying the endianness flag means that it is very easy for the
host side guys to do testing and not realise that the CODEC is the
one limiting the supported endians on the DAI link and thus miss
they have claimed to support endians they don't.

I believe you are right that there is a reasonable chance will see
some breakage after these patches, but that breakage should be
exposing host side bugs which we need to fix anyway.

> What i tried to demonstrate - is that if i set the unsupported
> endianness, i wouldn't expect that "the CODEC probably can care
> about the endian", as the message in [PATCH 00/38] suggests.

That comment in my original post was in respect to CODECs that
recieve/transmit audio directly over a SPI bus rather than a
normal audio bus. The is no standard governing how audio data is
transmitted over the SPI bus, thus endian could be important,
although I need to do some more work to analyse how people are
using these links. Often they are implemented effectively as a
CPU side DAI anyway.

Thanks,
Charles

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: Kirill Marinushkin <kmarinushkin@birdec.com>
Cc: <broonie@kernel.org>, <lgirdwood@gmail.com>,
	<codrin.ciubotariu@microchip.com>, <lars@metafoo.de>,
	<cychiang@chromium.org>, <tzungbi@google.com>,
	<bleung@chromium.org>, <matthias.bgg@gmail.com>,
	<oder_chiou@realtek.com>, <steven.eckhoff.opensource@gmail.com>,
	<srinivas.kandagatla@linaro.org>, <alexandre.belloni@bootlin.com>,
	<kuninori.morimoto.gx@renesas.com>, <jiaxin.yu@mediatek.com>,
	<alsa-devel@alsa-project.org>, <chrome-platform@lists.linux.dev>,
	<linux-mediatek@lists.infradead.org>,
	<patches@opensource.cirrus.com>
Subject: Re: [PATCH 01/38] ASoC: soc-component: Add comment for the endianness flag
Date: Tue, 10 May 2022 08:53:23 +0000	[thread overview]
Message-ID: <20220510085323.GA38351@ediswmail.ad.cirrus.com> (raw)
In-Reply-To: <901cb995-4a82-741e-00ea-a1c0b22ae749@birdec.com>

On Mon, May 09, 2022 at 09:22:42PM +0200, Kirill Marinushkin wrote:
> On 5/9/22 10:37 AM, Charles Keepax wrote:
> >On Sun, May 08, 2022 at 10:34:12PM +0200, Kirill Marinushkin wrote:
> >This sounds like an error on the CPU side of the DAI link rather
> >than the CODEC side of the DAI link. The formats that will be
> >supported on the link are the union of the CPU and CODEC supported
> >formats, ie. a format must be supported on both for the DAI to
> >support it.
> 
> Yes, agree, both sides of the DAI link should provide only
> endianness they support.
> 
> This works currently, but, from my understending, it will break,
> after we set `endianness = 1`.

It will break if the CPU side claims it supports endians which it
doesn't which I believe is what you have in your system.

> As soon as we start setting `endianness = 1`, the function
> `convert_endianness_formats()` will extend LE to (LE | BE), right?

Correct.

> If so, setting `endianness = 1` is the source of an error, right?

No, potentially it exposes an error but it is not the source of the
error. Endian should have no meaning once you cross an I2S bus.

> >If this is not the case then
> >the host I2S controller is claiming to support an endian it does
> >not, and the problem should be fixed on that side by removing the
> >supported endian.
> 
> I think we have a misundersanding of my example.
> 
> In my example, i don't mean, that my CPU part of the DAI link is broken.

Why are you sure the CPU part of the DAI link isn't broken? I2S
defines the order bits should be sent out on the bus, this means if
the CPU side recieves big endian or little endian data it doesn't
matter, the actual bus signals should be identical in both cases.
If only one endian works the actual signals on the bus must have
been different depending on which endian you played in which case
the host side doesn't match the I2S specification.

My point is that what you are seeing is exactly what you get if
your CPU DAI claimed to support both big and little endian but
just puts that data directly out on the bus, rather than adapting
to the endian of data it receives.

And to be fair this is exactly what I am trying to tackle with this
series. The fact we have so many CODECs that are incorrectly not
specifying the endianness flag means that it is very easy for the
host side guys to do testing and not realise that the CODEC is the
one limiting the supported endians on the DAI link and thus miss
they have claimed to support endians they don't.

I believe you are right that there is a reasonable chance will see
some breakage after these patches, but that breakage should be
exposing host side bugs which we need to fix anyway.

> What i tried to demonstrate - is that if i set the unsupported
> endianness, i wouldn't expect that "the CODEC probably can care
> about the endian", as the message in [PATCH 00/38] suggests.

That comment in my original post was in respect to CODECs that
recieve/transmit audio directly over a SPI bus rather than a
normal audio bus. The is no standard governing how audio data is
transmitted over the SPI bus, thus endian could be important,
although I need to do some more work to analyse how people are
using these links. Often they are implemented effectively as a
CPU side DAI anyway.

Thanks,
Charles

  parent reply	other threads:[~2022-05-10  8:54 UTC|newest]

Thread overview: 141+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-04 17:08 [PATCH 00/38] Clean up usage of the endianness flag Charles Keepax
2022-05-04 17:08 ` Charles Keepax
2022-05-04 17:08 ` Charles Keepax
2022-05-04 17:08 ` [PATCH 01/38] ASoC: soc-component: Add comment for " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-08 20:34   ` Kirill Marinushkin
2022-05-08 20:34     ` Kirill Marinushkin
2022-05-08 20:34     ` Kirill Marinushkin
2022-05-09  8:37     ` Charles Keepax
2022-05-09  8:37       ` Charles Keepax
2022-05-09  8:37       ` Charles Keepax
2022-05-09 19:22       ` Kirill Marinushkin
2022-05-09 19:22         ` Kirill Marinushkin
2022-05-09 19:22         ` Kirill Marinushkin
2022-05-09 19:30         ` Mark Brown
2022-05-09 19:30           ` Mark Brown
2022-05-09 19:30           ` Mark Brown
2022-05-09 20:11           ` Kirill Marinushkin
2022-05-09 20:11             ` Kirill Marinushkin
2022-05-09 20:11             ` Kirill Marinushkin
2022-05-09 20:18             ` Mark Brown
2022-05-09 20:18               ` Mark Brown
2022-05-09 20:18               ` Mark Brown
2022-05-10  8:53         ` Charles Keepax [this message]
2022-05-10  8:53           ` Charles Keepax
2022-05-10  8:53           ` Charles Keepax
2022-05-04 17:08 ` [PATCH 02/38] ASoC: atmel-pdmic: Remove endianness flag on pdmic component Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 03/38] ASoC: atmel-classd: Remove endianness flag on class d component Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 04/38] ASoC: cs4270: Remove redundant big endian formats Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 05/38] ASoC: cs42l51: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 06/38] ASoC: cs4349: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 07/38] ASoC: hdmi-codec: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 08/38] ASoC: sta32x: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 09/38] ASoC: sta350: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 10/38] ASoC: hdac_hda: Add endianness flag in snd_soc_component_driver Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 11/38] ASoC: max98504: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 12/38] ASoC: adau1372: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 13/38] ASoC: cs4234: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 14/38] ASoC: cs35l41: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 15/38] ASoC: cx2072x: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 16/38] ASoC: lochnagar: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 17/38] ASoC: mt6351: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 18/38] ASoC: mt6358: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 19/38] ASoC: mt6359: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 20/38] ASoC: mt6660: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 21/38] ASoC: pcm3060: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 22/38] ASoC: rt1019: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 23/38] ASoC: rt9120: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 24/38] ASoC: tlv320adc3xxx: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 25/38] ASoC: tscs454: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 26/38] ASoC: cros_ec_codec: Add endianness flag in i2s_rx_component_driver Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 27/38] ASoC: wcd934x: Add endianness flag in snd_soc_component_driver Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 28/38] ASoC: wcd9335: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 29/38] ASoC: rt700: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 30/38] ASoC: rt711: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 31/38] ASoC: rt711-sdca: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08 ` [PATCH 32/38] ASoC: rt715: " Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:08   ` Charles Keepax
2022-05-04 17:09 ` [PATCH 33/38] ASoC: rt715-sdca: " Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09 ` [PATCH 34/38] ASoC: rt1308-sdw: " Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09 ` [PATCH 35/38] ASoC: rt1316-sdw: " Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09 ` [PATCH 36/38] ASoC: wcd938x: " Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09 ` [PATCH 37/38] ASoC: wsa881x: " Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09 ` [PATCH 38/38] ASoC: sdw-mockup: " Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-04 17:09   ` Charles Keepax
2022-05-10 11:13 ` [PATCH 00/38] Clean up usage of the endianness flag Mark Brown
2022-05-10 11:13   ` Mark Brown
2022-05-10 11:13   ` Mark Brown

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