From: Herve Codina <herve.codina@bootlin.com> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Nicolas Ferre <nicolas.ferre@microchip.com>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Claudiu Beznea <claudiu.beznea@microchip.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Horatiu Vultur <horatiu.vultur@microchip.com> Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Herve Codina <herve.codina@bootlin.com> Subject: [PATCH 1/3] clk: lan966x: Fix the lan966x clock gate register address Date: Fri, 13 May 2022 12:58:48 +0200 [thread overview] Message-ID: <20220513105850.310375-2-herve.codina@bootlin.com> (raw) In-Reply-To: <20220513105850.310375-1-herve.codina@bootlin.com> The register address used for the clock gate register is the base register address coming from first reg map (ie. the generic clock registers) instead of the second reg map defining the clock gate register. Use the correct clock gate register address. Fixes: 5ad5915dea00 ("clk: lan966x: Extend lan966x clock driver for clock gating support") Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- drivers/clk/clk-lan966x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-lan966x.c b/drivers/clk/clk-lan966x.c index d1535ac13e89..81cb90955d68 100644 --- a/drivers/clk/clk-lan966x.c +++ b/drivers/clk/clk-lan966x.c @@ -213,7 +213,7 @@ static int lan966x_gate_clk_register(struct device *dev, hw_data->hws[i] = devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name, - "lan966x", 0, base, + "lan966x", 0, gate_base, clk_gate_desc[idx].bit_idx, 0, &clk_gate_lock); -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Herve Codina <herve.codina@bootlin.com> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Nicolas Ferre <nicolas.ferre@microchip.com>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Claudiu Beznea <claudiu.beznea@microchip.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Horatiu Vultur <horatiu.vultur@microchip.com> Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Herve Codina <herve.codina@bootlin.com> Subject: [PATCH 1/3] clk: lan966x: Fix the lan966x clock gate register address Date: Fri, 13 May 2022 12:58:48 +0200 [thread overview] Message-ID: <20220513105850.310375-2-herve.codina@bootlin.com> (raw) In-Reply-To: <20220513105850.310375-1-herve.codina@bootlin.com> The register address used for the clock gate register is the base register address coming from first reg map (ie. the generic clock registers) instead of the second reg map defining the clock gate register. Use the correct clock gate register address. Fixes: 5ad5915dea00 ("clk: lan966x: Extend lan966x clock driver for clock gating support") Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- drivers/clk/clk-lan966x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-lan966x.c b/drivers/clk/clk-lan966x.c index d1535ac13e89..81cb90955d68 100644 --- a/drivers/clk/clk-lan966x.c +++ b/drivers/clk/clk-lan966x.c @@ -213,7 +213,7 @@ static int lan966x_gate_clk_register(struct device *dev, hw_data->hws[i] = devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name, - "lan966x", 0, base, + "lan966x", 0, gate_base, clk_gate_desc[idx].bit_idx, 0, &clk_gate_lock); -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-13 10:59 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-13 10:58 [PATCH 0/3] Microchip LAN966x USB device support Herve Codina 2022-05-13 10:58 ` Herve Codina 2022-05-13 10:58 ` Herve Codina [this message] 2022-05-13 10:58 ` [PATCH 1/3] clk: lan966x: Fix the lan966x clock gate register address Herve Codina 2022-05-13 10:58 ` [PATCH 2/3] dt-bindings: usb: atmel: Add Microchip LAN966x compatible string Herve Codina 2022-05-13 10:58 ` Herve Codina 2022-05-13 12:57 ` Krzysztof Kozlowski 2022-05-13 12:57 ` Krzysztof Kozlowski 2022-05-20 11:34 ` Herve Codina 2022-05-20 11:34 ` Herve Codina 2022-05-20 11:40 ` Krzysztof Kozlowski 2022-05-20 11:40 ` Krzysztof Kozlowski 2022-05-20 12:21 ` Herve Codina 2022-05-20 12:21 ` Herve Codina 2022-05-20 12:50 ` Krzysztof Kozlowski 2022-05-20 12:50 ` Krzysztof Kozlowski 2022-05-20 13:02 ` Herve Codina 2022-05-20 13:02 ` Herve Codina 2022-05-20 13:38 ` Krzysztof Kozlowski 2022-05-20 13:38 ` Krzysztof Kozlowski 2022-05-20 13:52 ` Alexandre Belloni 2022-05-20 13:52 ` Alexandre Belloni 2022-05-20 14:05 ` Krzysztof Kozlowski 2022-05-20 14:05 ` Krzysztof Kozlowski 2022-05-20 14:12 ` Herve Codina 2022-05-20 14:12 ` Herve Codina 2022-05-13 10:58 ` [PATCH 3/3] ARM: dts: lan966x: Add UDPHS support Herve Codina 2022-05-13 10:58 ` Herve Codina 2022-05-13 12:54 ` Krzysztof Kozlowski 2022-05-13 12:54 ` Krzysztof Kozlowski 2022-05-20 12:37 ` Herve Codina 2022-05-20 12:37 ` Herve Codina 2022-05-20 12:48 ` Krzysztof Kozlowski 2022-05-20 12:48 ` Krzysztof Kozlowski 2022-05-14 9:35 ` Sergei Shtylyov 2022-05-14 9:35 ` Sergei Shtylyov 2022-05-20 15:23 [PATCH 0/3] Microchip LAN966x USB device support Herve Codina 2022-05-20 15:23 ` [PATCH 1/3] clk: lan966x: Fix the lan966x clock gate register address Herve Codina 2022-05-20 15:23 ` Herve Codina
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