From: Ravi Bangoria <ravi.bangoria@amd.com>
To: <peterz@infradead.org>, <acme@kernel.org>
Cc: <ravi.bangoria@amd.com>, <jolsa@kernel.org>,
<namhyung@kernel.org>, <eranian@google.com>, <irogers@google.com>,
<jmario@redhat.com>, <leo.yan@linaro.org>, <alisaidi@amazon.com>,
<ak@linux.intel.com>, <kan.liang@linux.intel.com>,
<dave.hansen@linux.intel.com>, <hpa@zytor.com>,
<mingo@redhat.com>, <mark.rutland@arm.com>,
<alexander.shishkin@linux.intel.com>, <tglx@linutronix.de>,
<bp@alien8.de>, <x86@kernel.org>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <sandipan.das@amd.com>,
<ananth.narayan@amd.com>, <kim.phillips@amd.com>,
<santosh.shukla@amd.com>
Subject: [PATCH 02/13] perf/x86/amd: Add IBS OP_DATA2/3 register bit definitions
Date: Wed, 25 May 2022 15:09:27 +0530 [thread overview]
Message-ID: <20220525093938.4101-3-ravi.bangoria@amd.com> (raw)
In-Reply-To: <20220525093938.4101-1-ravi.bangoria@amd.com>
AMD IBS OP_DATA2 and OP_DATA3 provides detail about tagged load/store
ops. Add definitions for these registers into header file. In addition
to those, IBS_OP_DATA2 DataSrc provides detail about location of the
data being accessed from by load ops. Define macros for legacy and
extended DataSrc values.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
---
arch/x86/include/asm/amd-ibs.h | 76 ++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
index aabdbb5ab920..22184fe20cf0 100644
--- a/arch/x86/include/asm/amd-ibs.h
+++ b/arch/x86/include/asm/amd-ibs.h
@@ -6,6 +6,82 @@
#include <asm/msr-index.h>
+/* IBS_OP_DATA2 Bits */
+#define IBS_DATA_SRC_HI_SHIFT 6
+#define IBS_DATA_SRC_HI_MASK (0x3ULL << IBS_DATA_SRC_HI_SHIFT)
+#define IBS_CACHE_HIT_ST_SHIFT 5
+#define IBS_CACHE_HIT_ST_MASK (0x1ULL << IBS_CACHE_HIT_ST_SHIFT)
+#define IBS_RMT_NODE_SHIFT 4
+#define IBS_RMT_NODE_MASK (0x1ULL << IBS_RMT_NODE_SHIFT)
+#define IBS_DATA_SRC_LO_SHIFT 0
+#define IBS_DATA_SRC_LO_MASK (0x7ULL << IBS_DATA_SRC_LO_SHIFT)
+
+/* IBS_OP_DATA2 DataSrc */
+#define IBS_DATA_SRC_LOC_CACHE 2
+#define IBS_DATA_SRC_DRAM 3
+#define IBS_DATA_SRC_REM_CACHE 4
+#define IBS_DATA_SRC_IO 7
+
+/* IBS_OP_DATA2 with DataSrc Extension */
+#define IBS_DATA_SRC_EXT_LOC_CACHE 1
+#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2
+#define IBS_DATA_SRC_EXT_DRAM 3
+#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5
+#define IBS_DATA_SRC_EXT_PMEM 6
+#define IBS_DATA_SRC_EXT_IO 7
+#define IBS_DATA_SRC_EXT_EXT_MEM 8
+#define IBS_DATA_SRC_EXT_PEER_AGENT_MEM 12
+
+/* IBS_OP_DATA3 Bits */
+#define IBS_TLB_REFILL_LAT_SHIFT 48
+#define IBS_TLB_REFILL_LAT_MASK (0xFFFFULL << IBS_TLB_REFILL_LAT_SHIFT)
+#define IBS_DC_MISS_LAT_SHIFT 32
+#define IBS_DC_MISS_LAT_MASK (0xFFFFULL << IBS_DC_MISS_LAT_SHIFT)
+#define IBS_OP_DC_MISS_OPEN_MEM_REQS_SHIFT 26
+#define IBS_OP_DC_MISS_OPEN_MEM_REQS_MASK (0x3FULL << IBS_OP_DC_MISS_OPEN_MEM_REQS_SHIFT)
+#define IBS_OP_MEM_WIDTH_SHIFT 22
+#define IBS_OP_MEM_WIDTH_MASK (0xFULL << IBS_OP_MEM_WIDTH_SHIFT)
+#define IBS_SW_PF_SHIFT 21
+#define IBS_SW_PF_MASK (0x1ULL << IBS_SW_PF_SHIFT)
+#define IBS_L2_MISS_SHIFT 20
+#define IBS_L2_MISS_MASK (0x1ULL << IBS_L2_MISS_SHIFT)
+#define IBS_DC_L2_TLB_HIT_1G_SHIFT 19
+#define IBS_DC_L2_TLB_HIT_1G_MASK (0x1ULL << IBS_DC_L2_TLB_HIT_1G_SHIFT)
+#define IBS_DC_PHY_ADDR_VALID_SHIFT 18
+#define IBS_DC_PHY_ADDR_VALID_MASK (0x1ULL << IBS_DC_PHY_ADDR_VALID_SHIFT)
+#define IBS_DC_LIN_ADDR_VALID_SHIFT 17
+#define IBS_DC_LIN_ADDR_VALID_MASK (0x1ULL << IBS_DC_LIN_ADDR_VALID_SHIFT)
+#define IBS_DC_MISS_NO_MAB_ALLOC_SHIFT 16
+#define IBS_DC_MISS_NO_MAB_ALLOC_MASK (0x1ULL << IBS_DC_MISS_NO_MAB_ALLOC_SHIFT)
+#define IBS_DC_LOCKED_OP_SHIFT 15
+#define IBS_DC_LOCKED_OP_MASK (0x1ULL << IBS_DC_LOCKED_OP_SHIFT)
+#define IBS_DC_UC_MEM_ACC_SHIFT 14
+#define IBS_DC_UC_MEM_ACC_MASK (0x1ULL << IBS_DC_UC_MEM_ACC_SHIFT)
+#define IBS_DC_WC_MEM_ACC_SHIFT 13
+#define IBS_DC_WC_MEM_ACC_MASK (0x1ULL << IBS_DC_WC_MEM_ACC_SHIFT)
+#define IBS_DC_MIS_ACC_SHIFT 8
+#define IBS_DC_MIS_ACC_MASK (0x1ULL << IBS_DC_MIS_ACC_SHIFT)
+#define IBS_DC_MISS_SHIFT 7
+#define IBS_DC_MISS_MASK (0x1ULL << IBS_DC_MISS_SHIFT)
+#define IBS_DC_L2_TLB_HIT_2M_SHIFT 6
+#define IBS_DC_L2_TLB_HIT_2M_MASK (0x1ULL << IBS_DC_L2_TLB_HIT_2M_SHIFT)
+/*
+ * Definition of 5-4 bits is different between Zen3 and Zen4 (Zen2 definition
+ * is same as Zen4) but the end result is same. So using Zen4 definition here.
+ */
+#define IBS_DC_L1_TLB_HIT_1G_SHIFT 5
+#define IBS_DC_L1_TLB_HIT_1G_MASK (0x1ULL << IBS_DC_L1_TLB_HIT_1G_SHIFT)
+#define IBS_DC_L1_TLB_HIT_2M_SHIFT 4
+#define IBS_DC_L1_TLB_HIT_2M_MASK (0x1ULL << IBS_DC_L1_TLB_HIT_2M_SHIFT)
+#define IBS_DC_L2_TLB_MISS_SHIFT 3
+#define IBS_DC_L2_TLB_MISS_MASK (0x1ULL << IBS_DC_L2_TLB_MISS_SHIFT)
+#define IBS_DC_L1_TLB_MISS_SHIFT 2
+#define IBS_DC_L1_TLB_MISS_MASK (0x1ULL << IBS_DC_L1_TLB_MISS_SHIFT)
+#define IBS_ST_OP_SHIFT 1
+#define IBS_ST_OP_MASK (0x1ULL << IBS_ST_OP_SHIFT)
+#define IBS_LD_OP_SHIFT 0
+#define IBS_LD_OP_MASK (0x1ULL << IBS_LD_OP_SHIFT)
+
/*
* IBS Hardware MSRs
*/
--
2.31.1
next prev parent reply other threads:[~2022-05-25 9:42 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-25 9:39 [PATCH 00/13] perf mem/c2c: Add support for AMD Ravi Bangoria
2022-05-25 9:39 ` [PATCH 01/13] perf/mem: Introduce PERF_MEM_LVLNUM_{EXTN_MEM|IO} Ravi Bangoria
2022-05-25 9:39 ` Ravi Bangoria [this message]
2022-05-26 15:08 ` [PATCH 02/13] perf/x86/amd: Add IBS OP_DATA2/3 register bit definitions Kim Phillips
2022-06-01 4:25 ` Ravi Bangoria
2022-05-25 9:39 ` [PATCH 03/13] perf/x86/amd: Support PERF_SAMPLE_DATA_SRC based on IBS_OP_DATA* Ravi Bangoria
2022-05-25 9:39 ` [PATCH 04/13] perf/x86/amd: Support PERF_SAMPLE_WEIGHT using IBS OP_DATA3[IbsDcMissLat] Ravi Bangoria
2022-05-25 12:58 ` Stephane Eranian
2022-05-26 12:14 ` Ravi Bangoria
2022-05-25 9:39 ` [PATCH 05/13] perf/x86/amd: Support PERF_SAMPLE_ADDR using IBS_DC_LINADDR Ravi Bangoria
2022-05-25 9:39 ` [PATCH 06/13] perf/x86/amd: Support PERF_SAMPLE_PHY_ADDR using IBS_DC_PHYSADDR Ravi Bangoria
2022-05-25 11:21 ` Peter Zijlstra
2022-05-26 8:46 ` Ravi Bangoria
2022-05-26 9:56 ` Peter Zijlstra
2022-05-26 10:59 ` Ravi Bangoria
2022-05-26 11:09 ` Peter Zijlstra
2022-05-25 9:39 ` [PATCH 07/13] perf tool: Sync include/uapi/linux/perf_event.h header Ravi Bangoria
2022-05-25 9:39 ` [PATCH 08/13] perf tool: Sync arch/x86/include/asm/amd-ibs.h header Ravi Bangoria
2022-05-25 9:39 ` [PATCH 09/13] perf mem: Add support for printing PERF_MEM_LVLNUM_{EXTN_MEM|IO} Ravi Bangoria
2022-05-25 9:39 ` [PATCH 10/13] perf mem/c2c: Set PERF_SAMPLE_WEIGHT for LOAD_STORE events Ravi Bangoria
2022-05-25 9:39 ` [PATCH 11/13] perf mem/c2c: Add load store event mappings for AMD Ravi Bangoria
2022-05-25 9:39 ` [PATCH 12/13] perf mem/c2c: Avoid printing empty lines for unsupported events Ravi Bangoria
2022-05-25 9:39 ` [PATCH 13/13] perf mem: Use more generic term for LFB Ravi Bangoria
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