From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: balasubramani.vivekanandan@intel.com, dri-devel@lists.freedesktop.org Subject: [PATCH v5 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK Date: Wed, 1 Jun 2022 08:07:21 -0700 [thread overview] Message-ID: <20220601150725.521468-3-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220601150725.521468-1-matthew.d.roper@intel.com> Slice/subslice/EU information should be obtained via the topology queries provided by the I915_QUERY interface; let's turn off support for the old GETPARAM lookups on Xe_HP and beyond where we can't return meaningful values. The slice mask lookup is meaningless since Xe_HP doesn't support traditional slices (and we make no attempt to return the various new units like gslices, cslices, mslices, etc.) here. The subslice mask lookup is even more problematic; given the distinct masks for geometry vs compute purposes, the combined mask returned here is likely not what userspace would want to act upon anyway. The value is also limited to 32-bits by the nature of the GETPARAM ioctl which is sufficient for the initial Xe_HP platforms, but is unable to convey the larger masks that will be needed on other upcoming platforms. Finally, the value returned here becomes even less meaningful when used on multi-tile platforms where each tile will have its own masks. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> # mesa --- drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index c12a0adefda5..ac9767c56619 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, value = intel_engines_has_context_isolation(i915); break; case I915_PARAM_SLICE_MASK: + /* Not supported from Xe_HP onward; use topology queries */ + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) + return -EINVAL; + value = sseu->slice_mask; if (!value) return -ENODEV; break; case I915_PARAM_SUBSLICE_MASK: + /* Not supported from Xe_HP onward; use topology queries */ + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) + return -EINVAL; + /* Only copy bits from the first slice */ memcpy(&value, sseu->subslice_mask, min(sseu->ss_stride, (u8)sizeof(value))); -- 2.35.3
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v5 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK Date: Wed, 1 Jun 2022 08:07:21 -0700 [thread overview] Message-ID: <20220601150725.521468-3-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220601150725.521468-1-matthew.d.roper@intel.com> Slice/subslice/EU information should be obtained via the topology queries provided by the I915_QUERY interface; let's turn off support for the old GETPARAM lookups on Xe_HP and beyond where we can't return meaningful values. The slice mask lookup is meaningless since Xe_HP doesn't support traditional slices (and we make no attempt to return the various new units like gslices, cslices, mslices, etc.) here. The subslice mask lookup is even more problematic; given the distinct masks for geometry vs compute purposes, the combined mask returned here is likely not what userspace would want to act upon anyway. The value is also limited to 32-bits by the nature of the GETPARAM ioctl which is sufficient for the initial Xe_HP platforms, but is unable to convey the larger masks that will be needed on other upcoming platforms. Finally, the value returned here becomes even less meaningful when used on multi-tile platforms where each tile will have its own masks. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> # mesa --- drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index c12a0adefda5..ac9767c56619 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, value = intel_engines_has_context_isolation(i915); break; case I915_PARAM_SLICE_MASK: + /* Not supported from Xe_HP onward; use topology queries */ + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) + return -EINVAL; + value = sseu->slice_mask; if (!value) return -ENODEV; break; case I915_PARAM_SUBSLICE_MASK: + /* Not supported from Xe_HP onward; use topology queries */ + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) + return -EINVAL; + /* Only copy bits from the first slice */ memcpy(&value, sseu->subslice_mask, min(sseu->ss_stride, (u8)sizeof(value))); -- 2.35.3
next prev parent reply other threads:[~2022-06-01 15:08 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-01 15:07 [PATCH v5 0/6] i915: SSEU handling updates Matt Roper 2022-06-01 15:07 ` [Intel-gfx] " Matt Roper 2022-06-01 15:07 ` [PATCH v5 1/6] drm/i915/xehp: Use separate sseu init function Matt Roper 2022-06-01 15:07 ` [Intel-gfx] " Matt Roper 2022-06-01 15:07 ` Matt Roper [this message] 2022-06-01 15:07 ` [Intel-gfx] [PATCH v5 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK Matt Roper 2022-06-01 15:07 ` [PATCH v5 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling Matt Roper 2022-06-01 15:07 ` [Intel-gfx] " Matt Roper 2022-06-01 15:07 ` [PATCH v5 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format Matt Roper 2022-06-01 15:07 ` [Intel-gfx] " Matt Roper 2022-06-01 15:07 ` [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi Matt Roper 2022-06-01 15:07 ` [Intel-gfx] " Matt Roper 2022-06-01 15:07 ` [PATCH v5 6/6] drm/i915/pvc: Add SSEU changes Matt Roper 2022-06-01 15:07 ` [Intel-gfx] " Matt Roper 2022-06-01 15:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates Patchwork 2022-06-01 16:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-06-01 20:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2022-06-02 14:24 ` Matt Roper 2022-06-02 12:32 ` [PATCH v5 0/6] " Balasubramani Vivekanandan 2022-06-02 12:32 ` [Intel-gfx] " Balasubramani Vivekanandan
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