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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Joey Gouly <joey.gouly@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v5 00/27] arm64/sysreg: More system register generation
Date: Wed, 22 Jun 2022 18:43:49 +0100	[thread overview]
Message-ID: <20220622174416.1406282-1-broonie@kernel.org> (raw)

This series continues on with the conversion of the system registers to
automatic generation, together with a few cleanups and improvements that
were identified as part of looking through all the register definitions
and bringing them into line with the conventions we've been using.

v5:
 - Remove definition of AIVIVT cache type entirely, no longer
   referencing the constant.
 - Allow leading blanks on comments in the input file.
v4:
 - Rebase onto v5.19-rc3.
v3:
 - Fix value for ID_AA64ISAR2_EL1.WFxT IMP enumeration value.
 - Add conversions of LOR*_EL1, ID_AA64SMFR0_EL1 and ID_AA64ZFR0_EL1.
 - Rebase onto for-next/fixes due to the ID_AA64SMFR0_EL1 conversion.
v2:
 - Rework handling of AIVIVT so we just update the define to reflect the
   naming but don't change the user visible decode, the type was removed
   from v8 rather than being added in v9.

Mark Brown (27):
  arm64/cpuinfo: Remove refrences to reserved cache type
  arm64/sysreg: Allow leading blanks on comments in sysreg file
  arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h
  arm64/sysreg: Add SYS_FIELD_GET() helper
  arm64/sysreg: Standardise naming for CTR_EL0 fields
  arm64/sysreg: Standardise naming for DCZID_EL0 field names
  arm64/mte: Standardise GMID field name definitions
  arm64/sysreg: Align pointer auth enumeration defines with architecture
  arm64/sysreg: Make BHB clear feature defines match the architecture
  arm64/sysreg: Standardise naming for WFxT defines
  arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums
  arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields
  arm64/sysreg: Remove defines for RPRES enumeration
  arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names
  arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names
  arm64/sysreg: Convert CTR_EL0 to automatic generation
  arm64/sysreg: Convert DCZID_EL0 to automatic generation
  arm64/sysreg: Convert GMID to automatic generation
  arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation
  arm64/sysreg: Convert LORSA_EL1 to automatic generation
  arm64/sysreg: Convert LOREA_EL1 to automatic generation
  arm64/sysreg: Convert LORN_EL1 to automatic generation
  arm64/sysreg: Convert LORC_EL1 to automatic generation
  arm64/sysreg: Convert LORID_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation

 arch/arm64/include/asm/asm_pointer_auth.h     |   4 +-
 arch/arm64/include/asm/cache.h                |  29 +-
 arch/arm64/include/asm/cpufeature.h           |   2 +-
 arch/arm64/include/asm/el2_setup.h            |   2 +-
 arch/arm64/include/asm/gpr-num.h              |   3 +
 arch/arm64/include/asm/sysreg.h               | 126 +--------
 arch/arm64/kernel/alternative.c               |   2 +-
 arch/arm64/kernel/cpu_errata.c                |   2 +-
 arch/arm64/kernel/cpufeature.c                | 220 +++++++--------
 arch/arm64/kernel/cpuinfo.c                   |  31 +-
 arch/arm64/kernel/idreg-override.c            |  12 +-
 arch/arm64/kernel/traps.c                     |   6 +-
 .../arm64/kvm/hyp/include/nvhe/fixed_config.h |  32 +--
 arch/arm64/kvm/hyp/nvhe/sys_regs.c            |  12 +-
 arch/arm64/kvm/sys_regs.c                     |  14 +-
 arch/arm64/lib/mte.S                          |   2 +-
 arch/arm64/tools/gen-sysreg.awk               |   2 +-
 arch/arm64/tools/sysreg                       | 264 ++++++++++++++++++
 18 files changed, 456 insertions(+), 309 deletions(-)


base-commit: a111daf0c53ae91e71fd2bfe7497862d14132e3e
-- 
2.30.2


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             reply	other threads:[~2022-06-22 17:54 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-22 17:43 Mark Brown [this message]
2022-06-22 17:43 ` [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Mark Brown
2022-06-28 14:26   ` Will Deacon
2022-06-22 17:43 ` [PATCH v5 02/27] arm64/sysreg: Allow leading blanks on comments in sysreg file Mark Brown
2022-06-22 17:43 ` [PATCH v5 03/27] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h Mark Brown
2022-06-22 17:43 ` [PATCH v5 04/27] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
2022-06-22 17:43 ` [PATCH v5 05/27] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
2022-06-22 17:43 ` [PATCH v5 06/27] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
2022-06-22 17:43 ` [PATCH v5 07/27] arm64/mte: Standardise GMID field name definitions Mark Brown
2022-06-22 17:43 ` [PATCH v5 08/27] arm64/sysreg: Align pointer auth enumeration defines with architecture Mark Brown
2022-06-22 17:43 ` [PATCH v5 09/27] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
2022-06-22 17:43 ` [PATCH v5 10/27] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
2022-06-22 17:44 ` [PATCH v5 11/27] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
2022-06-22 17:44 ` [PATCH v5 12/27] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
2022-06-22 17:44 ` [PATCH v5 13/27] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
2022-06-22 17:44 ` [PATCH v5 14/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
2022-06-22 17:44 ` [PATCH v5 15/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 16/27] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
2022-06-22 17:44 ` [PATCH v5 17/27] arm64/sysreg: Convert DCZID_EL0 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 18/27] arm64/sysreg: Convert GMID " Mark Brown
2022-06-22 17:44 ` [PATCH v5 19/27] arm64/sysreg: Convert ID_AA64ISAR1_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 20/27] arm64/sysreg: Convert ID_AA64ISAR2_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 21/27] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 22/27] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 23/27] arm64/sysreg: Convert LORN_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 24/27] arm64/sysreg: Convert LORC_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 25/27] arm64/sysreg: Convert LORID_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 26/27] arm64/sysreg: Convert ID_AA64SMFR0_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 27/27] arm64/sysreg: Convert ID_AA64ZFR0_EL1 " Mark Brown

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