From: Mikko Perttunen <cyndis@kapsi.fi> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Dmitry Osipenko <digetx@gmail.com> Cc: Mikko Perttunen <mperttunen@nvidia.com>, Robin Murphy <robin.murphy@arm.com>, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7/v3 21/22] gpu: host1x: Use RESTART_W to skip timed out jobs on Tegra186+ Date: Mon, 27 Jun 2022 17:20:07 +0300 [thread overview] Message-ID: <20220627142008.2072474-22-cyndis@kapsi.fi> (raw) In-Reply-To: <20220627142008.2072474-1-cyndis@kapsi.fi> From: Mikko Perttunen <mperttunen@nvidia.com> When MLOCK enforcement is enabled, the 0-word write currently done is rejected by the hardware outside of an MLOCK region. As such, on these chips, which also have the newer, more convenient RESTART_W opcode, use that instead to skip over the timed out job. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> --- drivers/gpu/host1x/cdma.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/host1x/cdma.c b/drivers/gpu/host1x/cdma.c index 765e5aa64eb6..bb1f3c746be4 100644 --- a/drivers/gpu/host1x/cdma.c +++ b/drivers/gpu/host1x/cdma.c @@ -457,9 +457,24 @@ void host1x_cdma_update_sync_queue(struct host1x_cdma *cdma, * to offset 0xbad. This does nothing but * has a easily detected signature in debug * traces. + * + * On systems with MLOCK enforcement enabled, + * the above 0 word writes would fall foul of + * the enforcement. As such, in the first slot + * put a RESTART_W opcode to the beginning + * of the next job. We don't use this for older + * chips since those only support the RESTART + * opcode with inconvenient alignment requirements. */ - mapped[2*slot+0] = 0x1bad0000; - mapped[2*slot+1] = 0x1bad0000; + if (i == 0 && host1x->info->has_wide_gather) { + unsigned int next_job = (job->first_get/8 + job->num_slots) + % HOST1X_PUSHBUFFER_SLOTS; + mapped[2*slot+0] = (0xd << 28) | (next_job * 2); + mapped[2*slot+1] = 0x0; + } else { + mapped[2*slot+0] = 0x1bad0000; + mapped[2*slot+1] = 0x1bad0000; + } } job->cancelled = true; -- 2.36.1
WARNING: multiple messages have this Message-ID (diff)
From: Mikko Perttunen <cyndis@kapsi.fi> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Dmitry Osipenko <digetx@gmail.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Mikko Perttunen <mperttunen@nvidia.com>, linux-tegra@vger.kernel.org, Robin Murphy <robin.murphy@arm.com> Subject: [PATCH v7/v3 21/22] gpu: host1x: Use RESTART_W to skip timed out jobs on Tegra186+ Date: Mon, 27 Jun 2022 17:20:07 +0300 [thread overview] Message-ID: <20220627142008.2072474-22-cyndis@kapsi.fi> (raw) In-Reply-To: <20220627142008.2072474-1-cyndis@kapsi.fi> From: Mikko Perttunen <mperttunen@nvidia.com> When MLOCK enforcement is enabled, the 0-word write currently done is rejected by the hardware outside of an MLOCK region. As such, on these chips, which also have the newer, more convenient RESTART_W opcode, use that instead to skip over the timed out job. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> --- drivers/gpu/host1x/cdma.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/host1x/cdma.c b/drivers/gpu/host1x/cdma.c index 765e5aa64eb6..bb1f3c746be4 100644 --- a/drivers/gpu/host1x/cdma.c +++ b/drivers/gpu/host1x/cdma.c @@ -457,9 +457,24 @@ void host1x_cdma_update_sync_queue(struct host1x_cdma *cdma, * to offset 0xbad. This does nothing but * has a easily detected signature in debug * traces. + * + * On systems with MLOCK enforcement enabled, + * the above 0 word writes would fall foul of + * the enforcement. As such, in the first slot + * put a RESTART_W opcode to the beginning + * of the next job. We don't use this for older + * chips since those only support the RESTART + * opcode with inconvenient alignment requirements. */ - mapped[2*slot+0] = 0x1bad0000; - mapped[2*slot+1] = 0x1bad0000; + if (i == 0 && host1x->info->has_wide_gather) { + unsigned int next_job = (job->first_get/8 + job->num_slots) + % HOST1X_PUSHBUFFER_SLOTS; + mapped[2*slot+0] = (0xd << 28) | (next_job * 2); + mapped[2*slot+1] = 0x0; + } else { + mapped[2*slot+0] = 0x1bad0000; + mapped[2*slot+1] = 0x1bad0000; + } } job->cancelled = true; -- 2.36.1
next prev parent reply other threads:[~2022-06-27 14:20 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-27 14:19 [PATCH v7/v3 00/22] Host1x context isolation / Tegra234 support Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 01/22] dt-bindings: host1x: Add iommu-map property Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 02/22] gpu: host1x: Add context device management code Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 03/22] gpu: host1x: Program context stream ID on submission Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 04/22] arm64: tegra: Add Host1x context stream IDs on Tegra186+ Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 05/22] drm/tegra: falcon: Set DMACTX field on DMA transactions Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 06/22] drm/tegra: nvdec: Fix TRANSCFG register offset Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 07/22] drm/tegra: Support context isolation Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 08/22] drm/tegra: Implement stream ID related callbacks on engines Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 09/22] dt-bindings: Add bindings for Tegra234 Host1x and VIC Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-30 15:20 ` Rob Herring 2022-06-30 15:20 ` Rob Herring 2022-06-27 14:19 ` [PATCH v7/v3 10/22] dt-bindings: host1x: Fix bracketing in example Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-30 15:20 ` Rob Herring 2022-06-30 15:20 ` Rob Herring 2022-06-27 14:19 ` [PATCH v7/v3 11/22] dt-bindings: Add headers for Host1x and VIC on Tegra234 Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 12/22] arm64: tegra: Add " Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:19 ` [PATCH v7/v3 13/22] gpu: host1x: Deduplicate hardware headers Mikko Perttunen 2022-06-27 14:19 ` Mikko Perttunen 2022-06-27 14:20 ` [PATCH v7/v3 14/22] gpu: host1x: Simplify register mapping and add common aperture Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen 2022-06-27 14:20 ` [PATCH v7/v3 15/22] gpu: host1x: Program virtualization tables Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen 2022-06-27 14:20 ` [PATCH v7/v3 16/22] gpu: host1x: Allow reset to be missing Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen 2022-06-27 14:20 ` [PATCH v7/v3 17/22] gpu: host1x: Program interrupt destinations on Tegra234 Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen 2022-06-27 14:20 ` [PATCH v7/v3 18/22] gpu: host1x: Tegra234 device data and headers Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen 2022-06-27 14:20 ` [PATCH v7/v3 19/22] gpu: host1x: Rewrite job opcode sequence Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen 2022-06-27 14:20 ` [PATCH v7/v3 20/22] gpu: host1x: Add MLOCK release code on Tegra234 Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen [this message] 2022-06-27 14:20 ` [PATCH v7/v3 21/22] gpu: host1x: Use RESTART_W to skip timed out jobs on Tegra186+ Mikko Perttunen 2022-06-27 14:20 ` [PATCH v7/v3 22/22] drm/tegra: vic: Add Tegra234 support Mikko Perttunen 2022-06-27 14:20 ` Mikko Perttunen 2022-06-30 15:19 ` [PATCH v7/v3 00/22] Host1x context isolation / " Rob Herring 2022-06-30 15:19 ` Rob Herring
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