From: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> To: <miquel.raynal@bootlin.com>, <nagasure@xilinx.com>, <vigneshr@ti.com> Cc: <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <git@amd.com>, <richard@nod.at>, <amit.kumar-mahapatra@amd.com>, Olga Kitaina <okitain@gmail.com>, <stable@vger.kernel.org>, Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Subject: [PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR Date: Tue, 28 Jun 2022 21:18:24 +0530 [thread overview] Message-ID: <20220628154824.12222-3-amit.kumar-mahapatra@xilinx.com> (raw) In-Reply-To: <20220628154824.12222-1-amit.kumar-mahapatra@xilinx.com> From: Olga Kitaina <okitain@gmail.com> According to the Arasan NAND controller spec, the flash clock rate for SDR must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the CLK line for the mode. The driver previously always set 100 MHz for NV-DDR, which would result in incorrect behavior for NV-DDR modes 0-4. The appropriate clock rate can be calculated from the NV-DDR timing parameters as 1/tCK, or for rates measured in picoseconds, 10^12 / nand_nvddr_timings->tCK_min. Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller") CC: stable@vger.kernel.org # 5.8+ Signed-off-by: Olga Kitaina <okitain@gmail.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> --- drivers/mtd/nand/raw/arasan-nand-controller.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index c5264fa223c4..d4121d1243bf 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -1043,7 +1043,13 @@ static int anfc_setup_interface(struct nand_chip *chip, int target, DQS_BUFF_SEL_OUT(dqs_mode); } - anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; + if (nand_interface_is_sdr(conf)) { + anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; + } else { + /* ONFI timings are defined in picoseconds */ + anand->clk = div_u64((u64)NSEC_PER_SEC * 1000, + conf->timings.nvddr.tCK_min); + } /* * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> To: <miquel.raynal@bootlin.com>, <nagasure@xilinx.com>, <vigneshr@ti.com> Cc: <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <git@amd.com>, <richard@nod.at>, <amit.kumar-mahapatra@amd.com>, Olga Kitaina <okitain@gmail.com>, <stable@vger.kernel.org>, Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Subject: [PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR Date: Tue, 28 Jun 2022 21:18:24 +0530 [thread overview] Message-ID: <20220628154824.12222-3-amit.kumar-mahapatra@xilinx.com> (raw) In-Reply-To: <20220628154824.12222-1-amit.kumar-mahapatra@xilinx.com> From: Olga Kitaina <okitain@gmail.com> According to the Arasan NAND controller spec, the flash clock rate for SDR must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the CLK line for the mode. The driver previously always set 100 MHz for NV-DDR, which would result in incorrect behavior for NV-DDR modes 0-4. The appropriate clock rate can be calculated from the NV-DDR timing parameters as 1/tCK, or for rates measured in picoseconds, 10^12 / nand_nvddr_timings->tCK_min. Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller") CC: stable@vger.kernel.org # 5.8+ Signed-off-by: Olga Kitaina <okitain@gmail.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> --- drivers/mtd/nand/raw/arasan-nand-controller.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index c5264fa223c4..d4121d1243bf 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -1043,7 +1043,13 @@ static int anfc_setup_interface(struct nand_chip *chip, int target, DQS_BUFF_SEL_OUT(dqs_mode); } - anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; + if (nand_interface_is_sdr(conf)) { + anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; + } else { + /* ONFI timings are defined in picoseconds */ + anand->clk = div_u64((u64)NSEC_PER_SEC * 1000, + conf->timings.nvddr.tCK_min); + } /* * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work -- 2.17.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2022-06-28 15:48 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-28 15:48 [PATCH v3 0/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR Amit Kumar Mahapatra 2022-06-28 15:48 ` Amit Kumar Mahapatra 2022-06-28 15:48 ` [PATCH v3 1/2] mtd: rawnand: arasan: Update NAND bus clock instead of system clock Amit Kumar Mahapatra 2022-06-28 15:48 ` Amit Kumar Mahapatra 2022-06-29 11:38 ` Miquel Raynal 2022-06-29 11:38 ` Miquel Raynal 2022-06-28 15:48 ` Amit Kumar Mahapatra [this message] 2022-06-28 15:48 ` [PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR Amit Kumar Mahapatra 2022-06-29 11:38 ` Miquel Raynal 2022-06-29 11:38 ` Miquel Raynal
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