From: Christoph Hellwig <hch@lst.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, hch@lst.de, samuel@sholland.org,
atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr,
robh+dt@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, drew@beagleboard.org,
rdunlap@infradead.org, Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH v5 3/4] riscv: Implement Zicbom-based cache management operations
Date: Thu, 30 Jun 2022 06:28:30 +0200 [thread overview]
Message-ID: <20220630042830.GB4958@lst.de> (raw)
In-Reply-To: <20220629215944.397952-4-heiko@sntech.de>
On Wed, Jun 29, 2022 at 11:59:43PM +0200, Heiko Stuebner wrote:
> The Zicbom ISA-extension was ratified in november 2021
> and introduces instructions for dcache invalidate, clean
> and flush operations.
>
> Implement cache management operations based on them.
>
> Of course not all cores will support this, so implement an
> alternative-based mechanism that replaces empty instructions
> with ones done around Zicbom instructions.
>
> As discussed in previous versions, assume the platform
> being coherent by default so that non-coherent devices need
> to get marked accordingly by firmware.
The subject here seems somewhat odd. Yes, it does implement the
low-level cache management ops, but more importantly it adds
support for devices that are not DMA coherent.
Otherwise looks good:
Reviewed-by: Christoph Hellwig <hch@lst.de>
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, hch@lst.de, samuel@sholland.org,
atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr,
robh+dt@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, drew@beagleboard.org,
rdunlap@infradead.org, Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH v5 3/4] riscv: Implement Zicbom-based cache management operations
Date: Thu, 30 Jun 2022 06:28:30 +0200 [thread overview]
Message-ID: <20220630042830.GB4958@lst.de> (raw)
In-Reply-To: <20220629215944.397952-4-heiko@sntech.de>
On Wed, Jun 29, 2022 at 11:59:43PM +0200, Heiko Stuebner wrote:
> The Zicbom ISA-extension was ratified in november 2021
> and introduces instructions for dcache invalidate, clean
> and flush operations.
>
> Implement cache management operations based on them.
>
> Of course not all cores will support this, so implement an
> alternative-based mechanism that replaces empty instructions
> with ones done around Zicbom instructions.
>
> As discussed in previous versions, assume the platform
> being coherent by default so that non-coherent devices need
> to get marked accordingly by firmware.
The subject here seems somewhat odd. Yes, it does implement the
low-level cache management ops, but more importantly it adds
support for devices that are not DMA coherent.
Otherwise looks good:
Reviewed-by: Christoph Hellwig <hch@lst.de>
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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-06-30 4:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-29 21:59 [PATCH v5 0/4] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-06-29 21:59 ` Heiko Stuebner
2022-06-29 21:59 ` [PATCH v5 1/4] of: also handle dma-noncoherent in of_dma_is_coherent() Heiko Stuebner
2022-06-29 21:59 ` Heiko Stuebner
2022-06-30 4:25 ` Christoph Hellwig
2022-06-30 4:25 ` Christoph Hellwig
2022-06-30 14:57 ` Rob Herring
2022-06-30 14:57 ` Rob Herring
2022-06-29 21:59 ` [PATCH v5 2/4] dt-bindings: riscv: document cbom-block-size Heiko Stuebner
2022-06-29 21:59 ` Heiko Stuebner
2022-06-29 21:59 ` [PATCH v5 3/4] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-06-29 21:59 ` Heiko Stuebner
2022-06-30 4:28 ` Christoph Hellwig [this message]
2022-06-30 4:28 ` Christoph Hellwig
2022-06-29 21:59 ` [PATCH v5 4/4] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-06-29 21:59 ` Heiko Stuebner
2022-06-30 3:04 ` Guo Ren
2022-06-30 3:04 ` Guo Ren
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