From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de>, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register Date: Tue, 5 Jul 2022 12:43:20 +0300 [thread overview] Message-ID: <20220705094320.1313312-29-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20220705094320.1313312-1-dmitry.baryshkov@linaro.org> Other PHYs tables directly reference QPHY_PLL_LOCK_CHK_DLY_TIME register without using reglayout. Define corresponding register to be used by msm8996 PHY tables and use it directly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 - drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 4 +--- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +--- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 1 - drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 1 - 6 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 3f2c89ffee21..01e1d3f7538b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 4517f05fe45f..be6a94439b6c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, @@ -141,7 +140,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, [QPHY_COM_START_CONTROL] = 0x408, [QPHY_COM_PCS_READY_STATUS] = 0x448, - [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, [QPHY_SW_RESET] = 0x00, [QPHY_START_CTRL] = 0x08, [QPHY_PCS_STATUS] = 0x174, @@ -216,7 +214,7 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), - QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05), QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05), QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02), diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 59ba40c39ab3..2d65e1f56bfc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, @@ -148,7 +147,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, [QPHY_COM_START_CONTROL] = 0x408, [QPHY_COM_PCS_READY_STATUS] = 0x448, - [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, [QPHY_SW_RESET] = 0x00, [QPHY_START_CTRL] = 0x08, [QPHY_PCS_STATUS] = 0x174, @@ -435,7 +433,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), - QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h index 9593277cbd3a..c8515f506872 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -24,6 +24,7 @@ #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088 #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 +#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 #define QPHY_V2_PCS_FLL_CNTRL1 0x0c0 #define QPHY_V2_PCS_FLL_CNTRL2 0x0c4 #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 7ab129cd739b..c8583f5a54bd 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index ff1e10bfdea3..1d270356a97f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de>, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register Date: Tue, 5 Jul 2022 12:43:20 +0300 [thread overview] Message-ID: <20220705094320.1313312-29-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20220705094320.1313312-1-dmitry.baryshkov@linaro.org> Other PHYs tables directly reference QPHY_PLL_LOCK_CHK_DLY_TIME register without using reglayout. Define corresponding register to be used by msm8996 PHY tables and use it directly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 - drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 4 +--- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +--- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 1 - drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 1 - 6 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 3f2c89ffee21..01e1d3f7538b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 4517f05fe45f..be6a94439b6c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, @@ -141,7 +140,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, [QPHY_COM_START_CONTROL] = 0x408, [QPHY_COM_PCS_READY_STATUS] = 0x448, - [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, [QPHY_SW_RESET] = 0x00, [QPHY_START_CTRL] = 0x08, [QPHY_PCS_STATUS] = 0x174, @@ -216,7 +214,7 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), - QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05), QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05), QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02), diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 59ba40c39ab3..2d65e1f56bfc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, @@ -148,7 +147,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, [QPHY_COM_START_CONTROL] = 0x408, [QPHY_COM_PCS_READY_STATUS] = 0x448, - [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, [QPHY_SW_RESET] = 0x00, [QPHY_START_CTRL] = 0x08, [QPHY_PCS_STATUS] = 0x174, @@ -435,7 +433,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), - QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h index 9593277cbd3a..c8515f506872 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -24,6 +24,7 @@ #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088 #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 +#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 #define QPHY_V2_PCS_FLL_CNTRL1 0x0c0 #define QPHY_V2_PCS_FLL_CNTRL2 0x0c4 #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 7ab129cd739b..c8583f5a54bd 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index ff1e10bfdea3..1d270356a97f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -121,7 +121,6 @@ enum qphy_reg_layout { QPHY_COM_START_CONTROL, QPHY_COM_PCS_READY_STATUS, /* PCS registers */ - QPHY_PLL_LOCK_CHK_DLY_TIME, QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, -- 2.35.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2022-07-05 9:43 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-05 9:42 [PATCH v1 00/28] phy: qcom-qmp: split register tables Dmitry Baryshkov 2022-07-05 9:42 ` Dmitry Baryshkov 2022-07-05 9:42 ` [PATCH v1 01/28] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register Dmitry Baryshkov 2022-07-05 9:42 ` Dmitry Baryshkov 2022-07-05 9:42 ` [PATCH v1 02/28] phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table Dmitry Baryshkov 2022-07-05 9:42 ` Dmitry Baryshkov 2022-07-05 9:42 ` [PATCH v1 03/28] phy: qcom-qmp-combo,usb: add support for separate PCS_USB region Dmitry Baryshkov 2022-07-05 9:42 ` Dmitry Baryshkov 2022-07-05 9:42 ` [PATCH v1 04/28] phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3 Dmitry Baryshkov 2022-07-05 9:42 ` Dmitry Baryshkov 2022-07-05 9:42 ` [PATCH v1 05/28] phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines Dmitry Baryshkov 2022-07-05 9:42 ` Dmitry Baryshkov 2022-07-05 9:42 ` [PATCH v1 06/28] phy: qcom-qmp: rename QMP V2 PCS registers Dmitry Baryshkov 2022-07-05 9:42 ` Dmitry Baryshkov 2022-07-05 9:42 ` [PATCH v1 07/28] phy: qcom-qmp: use QPHY_V4_PCS for ipq6018/ipq8074 PCIe gen3 Dmitry Baryshkov 2022-07-05 9:42 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 08/28] phy: qcom-qmp: move QSERDES registers to separate header Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 09/28] phy: qcom-qmp: move QSERDES V3 registers to separate headers Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 10/28] phy: qcom-qmp: move QSERDES V4 " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 11/28] phy: qcom-qmp: move QSERDES V5 " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 12/28] phy: qcom-qmp: move QSERDES PLL registers to separate header Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 13/28] phy: qcom-qmp: move PCS V2 " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 14/28] phy: qcom-qmp: move PCS V3 registers to separate headers Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 15/28] phy: qcom-qmp: move PCS V4 " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 16/28] phy: qcom-qmp: move PCS V5 " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 17/28] phy: qcom-qmp: move PCIE QHP registers to separate header Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 18/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 19/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 20/28] phy: qcom-qmp: split PCS_UFS V3 symbols to separate header Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 21/28] phy: qcom-qmp: qserdes-com: add missing registers Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 22/28] phy: qcom-qmp: qserdes-com-v3: " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 23/28] phy: qcom-qmp: qserdes-com-v4: " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 24/28] phy: qcom-qmp: qserdes-com-v5: " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 25/28] phy: qcom-qmp: pcs-v3: " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 26/28] phy: qcom-qmp: pcs-pcie-v4: " Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` [PATCH v1 27/28] phy: qcom-qmp-usb: replace FLL layout writes for msm8996 Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov 2022-07-05 9:43 ` Dmitry Baryshkov [this message] 2022-07-05 9:43 ` [PATCH v1 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register Dmitry Baryshkov 2022-07-07 5:02 ` [PATCH v1 00/28] phy: qcom-qmp: split register tables Vinod Koul 2022-07-07 5:02 ` Vinod Koul
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