From: Ricardo Koller <ricarkol@google.com>
To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
andrew.jones@linux.dev
Cc: maz@kernel.org, alexandru.elisei@arm.com, eric.auger@redhat.com,
oliver.upton@linux.dev, reijiw@google.com,
Ricardo Koller <ricarkol@google.com>
Subject: [kvm-unit-tests PATCH v2 3/3] arm: pmu: Check for overflow in the low counter in chained counters tests
Date: Wed, 3 Aug 2022 11:23:28 -0700 [thread overview]
Message-ID: <20220803182328.2438598-4-ricarkol@google.com> (raw)
In-Reply-To: <20220803182328.2438598-1-ricarkol@google.com>
A chained event overflowing on the low counter can set the overflow flag
in PMOVS. KVM does not set it, but real HW and the fast-model seem to.
Moreover, the AArch64.IncrementEventCounter() pseudocode in the ARM ARM
(DDI 0487H.a, J1.1.1 "aarch64/debug") also sets the PMOVS bit on
overflow.
The pmu chain tests fail on bare metal when checking the overflow flag
of the low counter _not_ being set on overflow. Fix by checking for
overflow. Note that this test fails in KVM without the respective fix.
Signed-off-by: Ricardo Koller <ricarkol@google.com>
---
arm/pmu.c | 33 ++++++++++++++++++---------------
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/arm/pmu.c b/arm/pmu.c
index 7c5bc259..258780f4 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -583,7 +583,7 @@ static void test_chained_counters(void)
precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
report(read_regn_el0(pmevcntr, 1) == 1, "CHAIN counter #1 incremented");
- report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #1");
+ report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #1");
/* test 64b overflow */
@@ -595,7 +595,7 @@ static void test_chained_counters(void)
precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0));
report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2");
- report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #2");
+ report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #2");
write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
write_regn_el0(pmevcntr, 1, ALL_SET);
@@ -603,7 +603,7 @@ static void test_chained_counters(void)
precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0));
report(!read_regn_el0(pmevcntr, 1), "CHAIN counter #1 wrapped");
- report(read_sysreg(pmovsclr_el0) == 0x2, "overflow on chain counter");
+ report(read_sysreg(pmovsclr_el0) == 0x3, "overflow on even and odd counters");
}
static void test_chained_sw_incr(void)
@@ -629,8 +629,9 @@ static void test_chained_sw_incr(void)
write_sysreg(0x1, pmswinc_el0);
isb();
- report(!read_sysreg(pmovsclr_el0) && (read_regn_el0(pmevcntr, 1) == 1),
- "no overflow and chain counter incremented after 100 SW_INCR/CHAIN");
+ report((read_sysreg(pmovsclr_el0) == 0x1) &&
+ (read_regn_el0(pmevcntr, 1) == 1),
+ "overflow and chain counter incremented after 100 SW_INCR/CHAIN");
report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
@@ -648,10 +649,10 @@ static void test_chained_sw_incr(void)
write_sysreg(0x1, pmswinc_el0);
isb();
- report((read_sysreg(pmovsclr_el0) == 0x2) &&
+ report((read_sysreg(pmovsclr_el0) == 0x3) &&
(read_regn_el0(pmevcntr, 1) == 0) &&
(read_regn_el0(pmevcntr, 0) == 84),
- "overflow on chain counter and expected values after 100 SW_INCR/CHAIN");
+ "overflow on even and odd counters, and expected values after 100 SW_INCR/CHAIN");
report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
}
@@ -731,8 +732,9 @@ static void test_chain_promotion(void)
report_info("MEM_ACCESS counter #0 has value 0x%lx",
read_regn_el0(pmevcntr, 0));
- report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0),
- "CHAIN counter enabled: CHAIN counter was incremented and no overflow");
+ report((read_regn_el0(pmevcntr, 1) == 1) &&
+ (read_sysreg(pmovsclr_el0) == 0x1),
+ "CHAIN counter enabled: CHAIN counter was incremented and overflow");
report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx",
read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0));
@@ -759,8 +761,9 @@ static void test_chain_promotion(void)
report_info("MEM_ACCESS counter #0 has value 0x%lx",
read_regn_el0(pmevcntr, 0));
- report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0),
- "32b->64b: CHAIN counter incremented and no overflow");
+ report((read_regn_el0(pmevcntr, 1) == 1) &&
+ (read_sysreg(pmovsclr_el0) == 0x1),
+ "32b->64b: CHAIN counter incremented and overflow");
report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx",
read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0));
@@ -867,8 +870,8 @@ static void test_overflow_interrupt(void)
write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
isb();
mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E);
- report(expect_interrupts(0),
- "no overflow interrupt expected on 32b boundary");
+ report(expect_interrupts(0x1),
+ "expect overflow interrupt on 32b boundary");
/* overflow on odd counter */
pmu_reset_stats();
@@ -876,8 +879,8 @@ static void test_overflow_interrupt(void)
write_regn_el0(pmevcntr, 1, ALL_SET);
isb();
mem_access_loop(addr, 400, pmu.pmcr_ro | PMU_PMCR_E);
- report(expect_interrupts(0x2),
- "expect overflow interrupt on odd counter");
+ report(expect_interrupts(0x3),
+ "expect overflow interrupt on even and odd counter");
}
#endif
--
2.37.1.455.g008518b4e5-goog
WARNING: multiple messages have this Message-ID (diff)
From: Ricardo Koller <ricarkol@google.com>
To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
andrew.jones@linux.dev
Cc: maz@kernel.org
Subject: [kvm-unit-tests PATCH v2 3/3] arm: pmu: Check for overflow in the low counter in chained counters tests
Date: Wed, 3 Aug 2022 11:23:28 -0700 [thread overview]
Message-ID: <20220803182328.2438598-4-ricarkol@google.com> (raw)
In-Reply-To: <20220803182328.2438598-1-ricarkol@google.com>
A chained event overflowing on the low counter can set the overflow flag
in PMOVS. KVM does not set it, but real HW and the fast-model seem to.
Moreover, the AArch64.IncrementEventCounter() pseudocode in the ARM ARM
(DDI 0487H.a, J1.1.1 "aarch64/debug") also sets the PMOVS bit on
overflow.
The pmu chain tests fail on bare metal when checking the overflow flag
of the low counter _not_ being set on overflow. Fix by checking for
overflow. Note that this test fails in KVM without the respective fix.
Signed-off-by: Ricardo Koller <ricarkol@google.com>
---
arm/pmu.c | 33 ++++++++++++++++++---------------
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/arm/pmu.c b/arm/pmu.c
index 7c5bc259..258780f4 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -583,7 +583,7 @@ static void test_chained_counters(void)
precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
report(read_regn_el0(pmevcntr, 1) == 1, "CHAIN counter #1 incremented");
- report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #1");
+ report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #1");
/* test 64b overflow */
@@ -595,7 +595,7 @@ static void test_chained_counters(void)
precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0));
report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2");
- report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #2");
+ report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #2");
write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
write_regn_el0(pmevcntr, 1, ALL_SET);
@@ -603,7 +603,7 @@ static void test_chained_counters(void)
precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0));
report(!read_regn_el0(pmevcntr, 1), "CHAIN counter #1 wrapped");
- report(read_sysreg(pmovsclr_el0) == 0x2, "overflow on chain counter");
+ report(read_sysreg(pmovsclr_el0) == 0x3, "overflow on even and odd counters");
}
static void test_chained_sw_incr(void)
@@ -629,8 +629,9 @@ static void test_chained_sw_incr(void)
write_sysreg(0x1, pmswinc_el0);
isb();
- report(!read_sysreg(pmovsclr_el0) && (read_regn_el0(pmevcntr, 1) == 1),
- "no overflow and chain counter incremented after 100 SW_INCR/CHAIN");
+ report((read_sysreg(pmovsclr_el0) == 0x1) &&
+ (read_regn_el0(pmevcntr, 1) == 1),
+ "overflow and chain counter incremented after 100 SW_INCR/CHAIN");
report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
@@ -648,10 +649,10 @@ static void test_chained_sw_incr(void)
write_sysreg(0x1, pmswinc_el0);
isb();
- report((read_sysreg(pmovsclr_el0) == 0x2) &&
+ report((read_sysreg(pmovsclr_el0) == 0x3) &&
(read_regn_el0(pmevcntr, 1) == 0) &&
(read_regn_el0(pmevcntr, 0) == 84),
- "overflow on chain counter and expected values after 100 SW_INCR/CHAIN");
+ "overflow on even and odd counters, and expected values after 100 SW_INCR/CHAIN");
report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
}
@@ -731,8 +732,9 @@ static void test_chain_promotion(void)
report_info("MEM_ACCESS counter #0 has value 0x%lx",
read_regn_el0(pmevcntr, 0));
- report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0),
- "CHAIN counter enabled: CHAIN counter was incremented and no overflow");
+ report((read_regn_el0(pmevcntr, 1) == 1) &&
+ (read_sysreg(pmovsclr_el0) == 0x1),
+ "CHAIN counter enabled: CHAIN counter was incremented and overflow");
report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx",
read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0));
@@ -759,8 +761,9 @@ static void test_chain_promotion(void)
report_info("MEM_ACCESS counter #0 has value 0x%lx",
read_regn_el0(pmevcntr, 0));
- report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0),
- "32b->64b: CHAIN counter incremented and no overflow");
+ report((read_regn_el0(pmevcntr, 1) == 1) &&
+ (read_sysreg(pmovsclr_el0) == 0x1),
+ "32b->64b: CHAIN counter incremented and overflow");
report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx",
read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0));
@@ -867,8 +870,8 @@ static void test_overflow_interrupt(void)
write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
isb();
mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E);
- report(expect_interrupts(0),
- "no overflow interrupt expected on 32b boundary");
+ report(expect_interrupts(0x1),
+ "expect overflow interrupt on 32b boundary");
/* overflow on odd counter */
pmu_reset_stats();
@@ -876,8 +879,8 @@ static void test_overflow_interrupt(void)
write_regn_el0(pmevcntr, 1, ALL_SET);
isb();
mem_access_loop(addr, 400, pmu.pmcr_ro | PMU_PMCR_E);
- report(expect_interrupts(0x2),
- "expect overflow interrupt on odd counter");
+ report(expect_interrupts(0x3),
+ "expect overflow interrupt on even and odd counter");
}
#endif
--
2.37.1.455.g008518b4e5-goog
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next prev parent reply other threads:[~2022-08-03 18:23 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-03 18:23 [kvm-unit-tests PATCH v2 0/3] arm: pmu: Fixes for bare metal Ricardo Koller
2022-08-03 18:23 ` Ricardo Koller
2022-08-03 18:23 ` [kvm-unit-tests PATCH v2 1/3] arm: pmu: Add missing isb()'s after sys register writing Ricardo Koller
2022-08-03 18:23 ` Ricardo Koller
2022-08-04 8:55 ` Alexandru Elisei
2022-08-04 8:55 ` Alexandru Elisei
2022-08-05 0:42 ` Ricardo Koller
2022-08-05 0:42 ` Ricardo Koller
2022-08-03 18:23 ` [kvm-unit-tests PATCH v2 2/3] arm: pmu: Reset the pmu registers before starting some tests Ricardo Koller
2022-08-03 18:23 ` Ricardo Koller
2022-08-04 18:21 ` Eric Auger
2022-08-04 18:21 ` Eric Auger
2022-08-03 18:23 ` Ricardo Koller [this message]
2022-08-03 18:23 ` [kvm-unit-tests PATCH v2 3/3] arm: pmu: Check for overflow in the low counter in chained counters tests Ricardo Koller
2022-08-04 8:18 ` Andrew Jones
2022-08-04 8:18 ` Andrew Jones
2022-08-05 0:43 ` Ricardo Koller
2022-08-05 0:43 ` Ricardo Koller
2022-08-04 18:21 ` Eric Auger
2022-08-04 18:21 ` Eric Auger
2022-08-08 10:40 ` Marc Zyngier
2022-08-08 10:40 ` Marc Zyngier
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