From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Ben Widawsky <ben.widawsky@intel.com>
Subject: [PULL 07/12] hw/cxl: Fix wrong query of target ports
Date: Wed, 17 Aug 2022 16:06:13 -0400 [thread overview]
Message-ID: <20220817200536.350795-8-mst@redhat.com> (raw)
In-Reply-To: <20220817200536.350795-1-mst@redhat.com>
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Two issues were present in this code:
1) Check on which register to look in was inverted.
2) Both branches use the _LO register.
Whilst here moved to extract32() rather than hand rolling
the field extraction as simpler and hopefully less error prone.
Fixes Coverity CID: 1488873
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220808122051.14822-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/cxl/cxl-host.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index faa68ef038..1adf61231a 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -104,7 +104,6 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
uint32_t ctrl;
uint32_t ig_enc;
uint32_t iw_enc;
- uint32_t target_reg;
uint32_t target_idx;
ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
@@ -116,14 +115,13 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
- if (target_idx > 4) {
- target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
- target_reg >>= target_idx * 8;
+ if (target_idx < 4) {
+ *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO],
+ target_idx * 8, 8);
} else {
- target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
- target_reg >>= (target_idx - 4) * 8;
+ *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_HI],
+ (target_idx - 4) * 8, 8);
}
- *target = target_reg & 0xff;
return true;
}
--
MST
next prev parent reply other threads:[~2022-08-17 20:15 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-17 20:05 [PULL 00/12] pc,virtio: fixes Michael S. Tsirkin
2022-08-17 20:05 ` [PULL 01/12] virtio-scsi: fix race in virtio_scsi_dataplane_start() Michael S. Tsirkin
2022-08-17 20:05 ` [PULL 02/12] hw/virtio: gracefully handle unset vhost_dev vdev Michael S. Tsirkin
2022-08-17 20:05 ` [PULL 03/12] hw/virtio: handle un-configured shutdown in virtio-pci Michael S. Tsirkin
2022-08-17 20:06 ` [PULL 04/12] hw/virtio: fix vhost_user_read tracepoint Michael S. Tsirkin
2022-08-17 20:06 ` [PULL 05/12] x86: disable rng seeding via setup_data Michael S. Tsirkin
2022-08-17 20:06 ` [PULL 06/12] hw/cxl: Fix memory leak in error paths Michael S. Tsirkin
2022-08-17 20:06 ` Michael S. Tsirkin [this message]
2022-08-17 20:06 ` [PULL 08/12] hw/cxl: Add stub write function for RO MemoryRegionOps entries Michael S. Tsirkin
2022-08-17 20:06 ` [PULL 09/12] hw/cxl: Fix Get LSA input payload size which should be 8 bytes Michael S. Tsirkin
2022-08-17 20:06 ` [PULL 10/12] hw/cxl: Correctly handle variable sized mailbox input payloads Michael S. Tsirkin
2022-08-17 20:06 ` [PULL 11/12] tests: acpi: silence applesmc warning about invalid key Michael S. Tsirkin
2022-08-17 20:06 ` [PULL 12/12] virtio-pci: don't touch pci on virtio reset Michael S. Tsirkin
2022-08-18 15:35 ` [PULL 00/12] pc,virtio: fixes Richard Henderson
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