From: Conor Dooley <conor.dooley@microchip.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Conor Dooley <conor.dooley@microchip.com>, Daire McNamara <daire.mcnamara@microchip.com> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Claudiu Beznea <claudiu.beznea@microchip.com>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> Subject: [PATCH v4 00/13] PolarFire SoC reset controller & clock cleanups Date: Tue, 30 Aug 2022 13:50:58 +0100 [thread overview] Message-ID: <20220830125110.2372514-1-conor.dooley@microchip.com> (raw) Hey all, Kinda two things happening in this series, but I sent it together to ensure the second part would apply correctly. The first is the reset controller that I promised after discovering the issue triggered by CONFIG_PM & the phy not coming up correctly. I have now removed all the messing with resets from clock enable/disable functions & now use the aux bus to set up a reset controller driver. Since I needed something to test it, I hooked up the reset for the Cadence MACB on PolarFire SoC. This has been split into a second series for v2 (and is now in v6.0-rcN): https://lore.kernel.org/all/20220704114511.1892332-1-conor.dooley@microchip.com/ The second part adds rate control for the MSS PLL clock, followed by some simplifications to the driver & conversions of some custom structs to the corresponding structs in the framework. I'll take the dts patch myself when the rest of this is okay-ed. Thanks, Conor. Changes since v3: - return results directly in probe() & reset_controller_register() Changes since v2: - reorder reset Makefile/Kconfig entries - fix a pre-existing bug exposed by clang with this series applied - add Padmarao who co-authored the original driver to the authors Conor Dooley (13): clk: microchip: mpfs: fix clk_cfg array bounds violation dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: add reset controller reset: add polarfire soc reset support MAINTAINERS: add polarfire soc reset controller riscv: dts: microchip: add mpfs specific macb reset support clk: microchip: mpfs: add MSS pll's set & round rate clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: update module authorship & licencing .../bindings/clock/microchip,mpfs.yaml | 17 +- MAINTAINERS | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +- drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/clk-mpfs.c | 380 +++++++++--------- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 157 ++++++++ include/soc/microchip/mpfs.h | 8 + 9 files changed, 384 insertions(+), 196 deletions(-) create mode 100644 drivers/reset/reset-mpfs.c base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 -- 2.36.1
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Conor Dooley <conor.dooley@microchip.com>, Daire McNamara <daire.mcnamara@microchip.com> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Claudiu Beznea <claudiu.beznea@microchip.com>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> Subject: [PATCH v4 00/13] PolarFire SoC reset controller & clock cleanups Date: Tue, 30 Aug 2022 13:50:58 +0100 [thread overview] Message-ID: <20220830125110.2372514-1-conor.dooley@microchip.com> (raw) Hey all, Kinda two things happening in this series, but I sent it together to ensure the second part would apply correctly. The first is the reset controller that I promised after discovering the issue triggered by CONFIG_PM & the phy not coming up correctly. I have now removed all the messing with resets from clock enable/disable functions & now use the aux bus to set up a reset controller driver. Since I needed something to test it, I hooked up the reset for the Cadence MACB on PolarFire SoC. This has been split into a second series for v2 (and is now in v6.0-rcN): https://lore.kernel.org/all/20220704114511.1892332-1-conor.dooley@microchip.com/ The second part adds rate control for the MSS PLL clock, followed by some simplifications to the driver & conversions of some custom structs to the corresponding structs in the framework. I'll take the dts patch myself when the rest of this is okay-ed. Thanks, Conor. Changes since v3: - return results directly in probe() & reset_controller_register() Changes since v2: - reorder reset Makefile/Kconfig entries - fix a pre-existing bug exposed by clang with this series applied - add Padmarao who co-authored the original driver to the authors Conor Dooley (13): clk: microchip: mpfs: fix clk_cfg array bounds violation dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: add reset controller reset: add polarfire soc reset support MAINTAINERS: add polarfire soc reset controller riscv: dts: microchip: add mpfs specific macb reset support clk: microchip: mpfs: add MSS pll's set & round rate clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: update module authorship & licencing .../bindings/clock/microchip,mpfs.yaml | 17 +- MAINTAINERS | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +- drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/clk-mpfs.c | 380 +++++++++--------- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 157 ++++++++ include/soc/microchip/mpfs.h | 8 + 9 files changed, 384 insertions(+), 196 deletions(-) create mode 100644 drivers/reset/reset-mpfs.c base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 -- 2.36.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2022-08-30 12:51 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-30 12:50 Conor Dooley [this message] 2022-08-30 12:50 ` [PATCH v4 00/13] PolarFire SoC reset controller & clock cleanups Conor Dooley 2022-08-30 12:52 ` [PATCH v4 01/13] clk: microchip: mpfs: fix clk_cfg array bounds violation Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-08-31 17:03 ` Conor.Dooley 2022-08-31 17:03 ` Conor.Dooley 2022-09-08 6:44 ` Claudiu.Beznea 2022-09-08 6:44 ` Claudiu.Beznea 2022-09-08 6:48 ` Conor.Dooley 2022-09-08 6:48 ` Conor.Dooley 2022-09-09 11:01 ` Conor.Dooley 2022-09-09 11:01 ` Conor.Dooley 2022-08-30 12:52 ` [PATCH v4 02/13] dt-bindings: clk: microchip: mpfs: add reset controller support Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-08-30 12:52 ` [PATCH v4 03/13] clk: microchip: mpfs: add reset controller Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-09-08 6:45 ` Claudiu.Beznea 2022-09-08 6:45 ` Claudiu.Beznea 2022-08-30 12:52 ` [PATCH v4 04/13] reset: add polarfire soc reset support Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-09-08 6:44 ` Claudiu.Beznea 2022-09-08 6:44 ` Claudiu.Beznea 2022-08-30 12:52 ` [PATCH v4 05/13] MAINTAINERS: add polarfire soc reset controller Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-08-30 12:52 ` [PATCH v4 06/13] riscv: dts: microchip: add mpfs specific macb reset support Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-08-30 12:52 ` [PATCH v4 07/13] clk: microchip: mpfs: add MSS pll's set & round rate Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-09-08 6:46 ` Claudiu.Beznea 2022-09-08 6:46 ` Claudiu.Beznea 2022-08-30 12:52 ` [PATCH v4 08/13] clk: microchip: mpfs: move id & offset out of clock structs Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-09-08 6:46 ` Claudiu.Beznea 2022-09-08 6:46 ` Claudiu.Beznea 2022-08-30 12:52 ` [PATCH v4 09/13] clk: microchip: mpfs: simplify control reg access Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-09-08 6:46 ` Claudiu.Beznea 2022-09-08 6:46 ` Claudiu.Beznea 2022-08-30 12:52 ` [PATCH v4 10/13] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-09-08 6:47 ` Claudiu.Beznea 2022-09-08 6:47 ` Claudiu.Beznea 2022-08-30 12:52 ` [PATCH v4 11/13] clk: microchip: mpfs: convert cfg_clk to clk_divider Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-09-08 6:47 ` Claudiu.Beznea 2022-09-08 6:47 ` Claudiu.Beznea 2022-08-30 12:52 ` [PATCH v4 12/13] clk: microchip: mpfs: convert periph_clk to clk_gate Conor Dooley 2022-08-30 12:52 ` Conor Dooley 2022-09-08 6:47 ` Claudiu.Beznea 2022-09-08 6:47 ` Claudiu.Beznea 2022-08-30 12:52 ` [PATCH v4 13/13] clk: microchip: mpfs: update module authorship & licencing Conor Dooley 2022-08-30 12:52 ` Conor Dooley
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