From: Serge Semin <Sergey.Semin@baikalelectronics.ru> To: Michal Simek <michal.simek@xilinx.com>, Borislav Petkov <bp@alien8.de>, Mauro Carvalho Chehab <mchehab@kernel.org>, Tony Luck <tony.luck@intel.com>, James Morse <james.morse@arm.com>, Robert Richter <rric@kernel.org> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>, Serge Semin <fancer.lancer@gmail.com>, Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>, Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>, Manish Narani <manish.narani@xilinx.com>, Dinh Nguyen <dinguyen@kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH RESEND v2 02/18] EDAC/mc: Extend memtypes with LPDDR(mDDR) and LPDDR2 Date: Sat, 10 Sep 2022 22:49:51 +0300 [thread overview] Message-ID: <20220910195007.11027-3-Sergey.Semin@baikalelectronics.ru> (raw) In-Reply-To: <20220910195007.11027-1-Sergey.Semin@baikalelectronics.ru> These are normal memory types [1] which can be met on the real hardware. DW uMCTL2 DDRC IP-core can be configured to have them supported [2,3]. Let's extend the EDAC memory types enumeration with the corresponding IDs then. [1] https://en.wikipedia.org/wiki/LPDDR [2] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.501 [3] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.1717 Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/edac/edac_mc.c | 2 ++ include/linux/edac.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 634c41ea7804..e353e98e01e2 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -151,10 +151,12 @@ const char * const edac_mem_types[] = { [MEM_RDR] = "Registered-SDR", [MEM_DDR] = "Unbuffered-DDR", [MEM_RDDR] = "Registered-DDR", + [MEM_LPDDR] = "Low-Power-(m)DDR-RAM", [MEM_RMBS] = "RMBS", [MEM_DDR2] = "Unbuffered-DDR2", [MEM_FB_DDR2] = "FullyBuffered-DDR2", [MEM_RDDR2] = "Registered-DDR2", + [MEM_LPDDR2] = "Low-Power-DDR2-RAM", [MEM_XDR] = "XDR", [MEM_DDR3] = "Unbuffered-DDR3", [MEM_RDDR3] = "Registered-DDR3", diff --git a/include/linux/edac.h b/include/linux/edac.h index fa4bda2a70f6..89167a4459d5 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -157,6 +157,7 @@ static inline char *mc_event_error_type(const unsigned int err_type) * This is a variant of the DDR memories. * A registered memory has a buffer inside it, hiding * part of the memory details to the memory controller. + * @MEM_LPDDR: Low-Power DDR memory (mDDR). * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. * Those memories are labeled as "PC2-" instead of "PC" to @@ -167,6 +168,7 @@ static inline char *mc_event_error_type(const unsigned int err_type) * a chip select signal. * @MEM_RDDR2: Registered DDR2 RAM * This is a variant of the DDR2 memories. + * @MEM_LPDDR2: Low-Power DDR2 memory. * @MEM_XDR: Rambus XDR * It is an evolution of the original RAMBUS memories, * created to compete with DDR2. Weren't used on any @@ -199,10 +201,12 @@ enum mem_type { MEM_RDR, MEM_DDR, MEM_RDDR, + MEM_LPDDR, MEM_RMBS, MEM_DDR2, MEM_FB_DDR2, MEM_RDDR2, + MEM_LPDDR2, MEM_XDR, MEM_DDR3, MEM_RDDR3, @@ -230,10 +234,12 @@ enum mem_type { #define MEM_FLAG_RDR BIT(MEM_RDR) #define MEM_FLAG_DDR BIT(MEM_DDR) #define MEM_FLAG_RDDR BIT(MEM_RDDR) +#define MEM_FLAG_LPDDR BIT(MEM_LPDDR) #define MEM_FLAG_RMBS BIT(MEM_RMBS) #define MEM_FLAG_DDR2 BIT(MEM_DDR2) #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) +#define MEM_FLAG_LPDDR2 BIT(MEM_LPDDR2) #define MEM_FLAG_XDR BIT(MEM_XDR) #define MEM_FLAG_DDR3 BIT(MEM_DDR3) #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Serge Semin <Sergey.Semin@baikalelectronics.ru> To: Michal Simek <michal.simek@xilinx.com>, Borislav Petkov <bp@alien8.de>, Mauro Carvalho Chehab <mchehab@kernel.org>, Tony Luck <tony.luck@intel.com>, James Morse <james.morse@arm.com>, Robert Richter <rric@kernel.org> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>, Serge Semin <fancer.lancer@gmail.com>, Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>, Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>, Manish Narani <manish.narani@xilinx.com>, Dinh Nguyen <dinguyen@kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH RESEND v2 02/18] EDAC/mc: Extend memtypes with LPDDR(mDDR) and LPDDR2 Date: Sat, 10 Sep 2022 22:49:51 +0300 [thread overview] Message-ID: <20220910195007.11027-3-Sergey.Semin@baikalelectronics.ru> (raw) In-Reply-To: <20220910195007.11027-1-Sergey.Semin@baikalelectronics.ru> These are normal memory types [1] which can be met on the real hardware. DW uMCTL2 DDRC IP-core can be configured to have them supported [2,3]. Let's extend the EDAC memory types enumeration with the corresponding IDs then. [1] https://en.wikipedia.org/wiki/LPDDR [2] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.501 [3] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.1717 Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/edac/edac_mc.c | 2 ++ include/linux/edac.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 634c41ea7804..e353e98e01e2 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -151,10 +151,12 @@ const char * const edac_mem_types[] = { [MEM_RDR] = "Registered-SDR", [MEM_DDR] = "Unbuffered-DDR", [MEM_RDDR] = "Registered-DDR", + [MEM_LPDDR] = "Low-Power-(m)DDR-RAM", [MEM_RMBS] = "RMBS", [MEM_DDR2] = "Unbuffered-DDR2", [MEM_FB_DDR2] = "FullyBuffered-DDR2", [MEM_RDDR2] = "Registered-DDR2", + [MEM_LPDDR2] = "Low-Power-DDR2-RAM", [MEM_XDR] = "XDR", [MEM_DDR3] = "Unbuffered-DDR3", [MEM_RDDR3] = "Registered-DDR3", diff --git a/include/linux/edac.h b/include/linux/edac.h index fa4bda2a70f6..89167a4459d5 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -157,6 +157,7 @@ static inline char *mc_event_error_type(const unsigned int err_type) * This is a variant of the DDR memories. * A registered memory has a buffer inside it, hiding * part of the memory details to the memory controller. + * @MEM_LPDDR: Low-Power DDR memory (mDDR). * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. * Those memories are labeled as "PC2-" instead of "PC" to @@ -167,6 +168,7 @@ static inline char *mc_event_error_type(const unsigned int err_type) * a chip select signal. * @MEM_RDDR2: Registered DDR2 RAM * This is a variant of the DDR2 memories. + * @MEM_LPDDR2: Low-Power DDR2 memory. * @MEM_XDR: Rambus XDR * It is an evolution of the original RAMBUS memories, * created to compete with DDR2. Weren't used on any @@ -199,10 +201,12 @@ enum mem_type { MEM_RDR, MEM_DDR, MEM_RDDR, + MEM_LPDDR, MEM_RMBS, MEM_DDR2, MEM_FB_DDR2, MEM_RDDR2, + MEM_LPDDR2, MEM_XDR, MEM_DDR3, MEM_RDDR3, @@ -230,10 +234,12 @@ enum mem_type { #define MEM_FLAG_RDR BIT(MEM_RDR) #define MEM_FLAG_DDR BIT(MEM_DDR) #define MEM_FLAG_RDDR BIT(MEM_RDDR) +#define MEM_FLAG_LPDDR BIT(MEM_LPDDR) #define MEM_FLAG_RMBS BIT(MEM_RMBS) #define MEM_FLAG_DDR2 BIT(MEM_DDR2) #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) +#define MEM_FLAG_LPDDR2 BIT(MEM_LPDDR2) #define MEM_FLAG_XDR BIT(MEM_XDR) #define MEM_FLAG_DDR3 BIT(MEM_DDR3) #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-10 19:50 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-10 19:49 [PATCH RESEND v2 00/18] EDAC/synopsys: Add generic DDRC info and address mapping Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 01/18] EDAC/synopsys: Convert sysfs nodes to debugfs ones Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` Serge Semin [this message] 2022-09-10 19:49 ` [PATCH RESEND v2 02/18] EDAC/mc: Extend memtypes with LPDDR(mDDR) and LPDDR2 Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 03/18] EDAC/synopsys: Extend memtypes supported by controller Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 04/18] EDAC/synopsys: Detach private data from mci instance Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 05/18] EDAC/synopsys: Add DDRC basic parameters infrastructure Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 06/18] EDAC/synopsys: Convert plat-data to plat-init function Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 07/18] EDAC/synopsys: Parse ADDRMAP[7-8] CSRs for (LP)DDR4 only Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 08/18] EDAC/synopsys: Parse ADDRMAP[0] CSR for multi-ranks case only Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 09/18] EDAC/synopsys: Set actual DIMM ECC errors grain Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:49 ` [PATCH RESEND v2 10/18] EDAC/synopsys: Get corrected bit position Serge Semin 2022-09-10 19:49 ` Serge Semin 2022-09-10 19:50 ` [PATCH RESEND v2 11/18] EDAC/synopsys: Read full data pattern on errors Serge Semin 2022-09-10 19:50 ` Serge Semin 2022-09-10 19:50 ` [PATCH RESEND v2 12/18] EDAC/synopsys: Read data syndrome " Serge Semin 2022-09-10 19:50 ` Serge Semin 2022-09-10 19:50 ` [PATCH RESEND v2 13/18] EDAC/synopsys: Introduce System/SDRAM address translation interface Serge Semin 2022-09-10 19:50 ` Serge Semin 2022-09-10 19:50 ` [PATCH RESEND v2 14/18] EDAC/synopsys: Simplify HIF/SDRAM column mapping get procedure Serge Semin 2022-09-10 19:50 ` Serge Semin 2022-09-10 19:50 ` [PATCH RESEND v2 15/18] EDAC/synopsys: Add HIF/SDRAM mapping debugfs node Serge Semin 2022-09-10 19:50 ` Serge Semin 2022-09-10 19:50 ` [PATCH RESEND v2 16/18] EDAC/synopsys: Add erroneous page-frame/offset reporting Serge Semin 2022-09-10 19:50 ` Serge Semin 2022-09-10 19:50 ` [PATCH RESEND v2 17/18] EDAC/synopsys: Add system address regions support Serge Semin 2022-09-10 19:50 ` Serge Semin 2022-09-10 19:50 ` [PATCH RESEND v2 18/18] EDAC/synopsys: Add mapping-based memory size calculation Serge Semin 2022-09-10 19:50 ` Serge Semin
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