From: Vidya Sagar <vidyas@nvidia.com> To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>, <mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>, <ffclaire1224@gmail.com> Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com> Subject: [PATCH V2 2/9] PCI: tegra194: Drive CLKREQ signal low explicitly Date: Mon, 26 Sep 2022 17:20:31 +0530 [thread overview] Message-ID: <20220926115038.24727-3-vidyas@nvidia.com> (raw) In-Reply-To: <20220926115038.24727-1-vidyas@nvidia.com> Currently, the default setting is that CLKREQ signal of a Root Port is internally overridden to '0' to enable REFCLK flowing out to the slot. It is observed that one of the PCIe switches (case in point Broadcom PCIe Gen4 switch) is propagating the CLKREQ signal of the root port to the downstream side of the switch and expecting the endpoints to pull it low so that it (PCIe switch) can give out the REFCLK although the Switch as such doesn't support CLK-PM or ASPM-L1SS. So, as a work-around, this patch drives the CLKREQ of the Root Port itself low to avoid link up issues between PCIe switch downstream port and endpoints. This is not a wrong thing to do after all the CLKREQ is anyway being overridden to '0' internally and now it is just that the same is being propagated outside also. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 941fdb23e02f..7721f920dd74 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -46,6 +46,7 @@ #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE BIT(13) #define APPL_CTRL 0x4 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) @@ -1453,6 +1454,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, val = appl_readl(pcie, APPL_PINMUX); val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; + val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE; appl_writel(pcie, val, APPL_PINMUX); } -- 2.17.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com> To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>, <mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>, <ffclaire1224@gmail.com> Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com> Subject: [PATCH V2 2/9] PCI: tegra194: Drive CLKREQ signal low explicitly Date: Mon, 26 Sep 2022 17:20:31 +0530 [thread overview] Message-ID: <20220926115038.24727-3-vidyas@nvidia.com> (raw) In-Reply-To: <20220926115038.24727-1-vidyas@nvidia.com> Currently, the default setting is that CLKREQ signal of a Root Port is internally overridden to '0' to enable REFCLK flowing out to the slot. It is observed that one of the PCIe switches (case in point Broadcom PCIe Gen4 switch) is propagating the CLKREQ signal of the root port to the downstream side of the switch and expecting the endpoints to pull it low so that it (PCIe switch) can give out the REFCLK although the Switch as such doesn't support CLK-PM or ASPM-L1SS. So, as a work-around, this patch drives the CLKREQ of the Root Port itself low to avoid link up issues between PCIe switch downstream port and endpoints. This is not a wrong thing to do after all the CLKREQ is anyway being overridden to '0' internally and now it is just that the same is being propagated outside also. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 941fdb23e02f..7721f920dd74 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -46,6 +46,7 @@ #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE BIT(13) #define APPL_CTRL 0x4 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) @@ -1453,6 +1454,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, val = appl_readl(pcie, APPL_PINMUX); val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; + val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE; appl_writel(pcie, val, APPL_PINMUX); } -- 2.17.1
next prev parent reply other threads:[~2022-09-26 11:51 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-26 11:50 [PATCH V2 0/9] Enhancements to pcie-tegra194 driver Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar 2022-09-26 11:50 ` [PATCH V2 1/9] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar [this message] 2022-09-26 11:50 ` [PATCH V2 2/9] PCI: tegra194: Drive CLKREQ signal low explicitly Vidya Sagar 2022-09-26 11:50 ` [PATCH V2 3/9] PCI: tegra194: Fix polling delay for L2 state Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar 2022-09-26 11:50 ` [PATCH V2 4/9] PCI: tegra194: Handle errors in BPMP response Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar 2022-09-26 11:50 ` [PATCH V2 5/9] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar 2022-09-26 11:50 ` [PATCH V2 6/9] PCI: tegra194: Refactor LTSSM state polling on surprise down Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar 2022-09-26 18:16 ` Bjorn Helgaas 2022-09-26 18:16 ` Bjorn Helgaas 2022-09-26 11:50 ` [PATCH V2 7/9] PCI: tegra194: Disable direct speed change for EP Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar 2022-09-26 11:50 ` [PATCH V2 8/9] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar 2022-09-26 18:18 ` Bjorn Helgaas 2022-09-26 18:18 ` Bjorn Helgaas 2022-09-26 11:50 ` [PATCH V2 9/9] PCI: tegra194: Calibrate P2U for endpoint mode Vidya Sagar 2022-09-26 11:50 ` Vidya Sagar
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