From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: matthias.bgg@gmail.com
Cc: mturquette@baylibre.com, sboyd@kernel.org,
angelogioacchino.delregno@collabora.com, wenst@chromium.org,
miles.chen@mediatek.com, rex-bc.chen@mediatek.com,
nfraprado@collabora.com, chun-jie.chen@mediatek.com,
jose.exposito89@gmail.com, drinkcat@chromium.org,
weiyi.lu@mediatek.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Subject: [PATCH v3 01/10] arm64: dts: mt8183: Fix Mali GPU clock
Date: Tue, 27 Sep 2022 12:11:19 +0200 [thread overview]
Message-ID: <20220927101128.44758-2-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20220927101128.44758-1-angelogioacchino.delregno@collabora.com>
From: Chen-Yu Tsai <wenst@chromium.org>
The actual clock feeding into the Mali GPU on the MT8183 is from the
clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN
block, which itself is simply a pass-through placeholder for the MFGPLL
in the APMIXEDSYS block.
Fix the hardware description with the correct clock reference.
Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index a70b669c49ba..402136bfd535 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1678,7 +1678,7 @@ gpu: gpu@13040000 {
<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "job", "mmu", "gpu";
- clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+ clocks = <&mfgcfg CLK_MFG_BG3D>;
power-domains =
<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
--
2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: matthias.bgg@gmail.com
Cc: mturquette@baylibre.com, sboyd@kernel.org,
angelogioacchino.delregno@collabora.com, wenst@chromium.org,
miles.chen@mediatek.com, rex-bc.chen@mediatek.com,
nfraprado@collabora.com, chun-jie.chen@mediatek.com,
jose.exposito89@gmail.com, drinkcat@chromium.org,
weiyi.lu@mediatek.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Subject: [PATCH v3 01/10] arm64: dts: mt8183: Fix Mali GPU clock
Date: Tue, 27 Sep 2022 12:11:19 +0200 [thread overview]
Message-ID: <20220927101128.44758-2-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20220927101128.44758-1-angelogioacchino.delregno@collabora.com>
From: Chen-Yu Tsai <wenst@chromium.org>
The actual clock feeding into the Mali GPU on the MT8183 is from the
clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN
block, which itself is simply a pass-through placeholder for the MFGPLL
in the APMIXEDSYS block.
Fix the hardware description with the correct clock reference.
Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index a70b669c49ba..402136bfd535 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1678,7 +1678,7 @@ gpu: gpu@13040000 {
<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "job", "mmu", "gpu";
- clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+ clocks = <&mfgcfg CLK_MFG_BG3D>;
power-domains =
<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
--
2.37.2
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next prev parent reply other threads:[~2022-09-27 10:11 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 10:11 [PATCH v3 00/10] MediaTek SoC safe clock muxing and GPU clocks AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno [this message]
2022-09-27 10:11 ` [PATCH v3 01/10] arm64: dts: mt8183: Fix Mali GPU clock AngeloGioacchino Del Regno
2022-12-06 18:30 ` Nícolas F. R. A. Prado
2022-12-06 18:30 ` Nícolas F. R. A. Prado
2022-12-16 10:46 ` Matthias Brugger
2022-12-16 10:46 ` Matthias Brugger
2022-12-16 11:23 ` Matthias Brugger
2022-12-16 11:23 ` Matthias Brugger
2022-09-27 10:11 ` [PATCH v3 02/10] clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-27 10:11 ` [PATCH v3 03/10] clk: mediatek: mux: add clk notifier functions AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-27 10:11 ` [PATCH v3 04/10] clk: mediatek: mt8183: Add clk mux notifier for MFG mux AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-27 10:11 ` [PATCH v3 05/10] clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-27 10:11 ` [PATCH v3 06/10] clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-27 10:11 ` [PATCH v3 07/10] clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-27 10:11 ` [PATCH v3 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-30 5:59 ` MandyJH Liu (劉人僖)
2022-09-30 5:59 ` MandyJH Liu (劉人僖)
2022-09-30 8:29 ` AngeloGioacchino Del Regno
2022-09-30 8:29 ` AngeloGioacchino Del Regno
2022-09-30 8:44 ` Chen-Yu Tsai
2022-09-30 8:44 ` Chen-Yu Tsai
2022-09-30 8:58 ` AngeloGioacchino Del Regno
2022-09-30 8:58 ` AngeloGioacchino Del Regno
2022-09-30 9:02 ` Chen-Yu Tsai
2022-09-30 9:02 ` Chen-Yu Tsai
2022-09-30 9:04 ` AngeloGioacchino Del Regno
2022-09-30 9:04 ` AngeloGioacchino Del Regno
2022-09-30 9:07 ` Chen-Yu Tsai
2022-09-30 9:07 ` Chen-Yu Tsai
2022-09-27 10:11 ` [PATCH v3 09/10] clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-27 10:11 ` [PATCH v3 10/10] clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel AngeloGioacchino Del Regno
2022-09-27 10:11 ` AngeloGioacchino Del Regno
2022-09-29 4:24 ` [PATCH v3 00/10] MediaTek SoC safe clock muxing and GPU clocks Chen-Yu Tsai
2022-09-29 4:24 ` Chen-Yu Tsai
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