From: Serge Semin <Sergey.Semin@baikalelectronics.ru> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michal Simek <michal.simek@xilinx.com>, Borislav Petkov <bp@alien8.de>, Mauro Carvalho Chehab <mchehab@kernel.org>, Tony Luck <tony.luck@intel.com>, James Morse <james.morse@arm.com>, Robert Richter <rric@kernel.org> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>, Serge Semin <fancer.lancer@gmail.com>, Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>, Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>, Manish Narani <manish.narani@xilinx.com>, Dinh Nguyen <dinguyen@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v3 04/13] EDAC/synopsys: Add optional ECC Scrub support Date: Fri, 30 Sep 2022 02:41:12 +0300 [thread overview] Message-ID: <20220929234121.13955-5-Sergey.Semin@baikalelectronics.ru> (raw) In-Reply-To: <20220929234121.13955-1-Sergey.Semin@baikalelectronics.ru> DW uMCTL2 DDRC ECC has a so called ECC Scrub feature in case if an single-bit error is detected. The scrub is executed as a new RMW operation to the location that resulted in a single-bit error thus fixing the ECC code preserved in the SDRAM. But that feature not only optional, but also runtime switchable. So there can be platforms with DW uMCTL2 DDRC not supporting hardware-base scrub. In those cases the single-bit errors will still be detected but won't be fixed until the next SDRAM write commands to the erroneous location. Since the ECC Scrub feature availability is detectable by means of the ECCCFG0.dis_scrub flag state we can use it to tune the MCI core up so one would automatically execute the platform-specific the platform-specific scrubbing to the affected SDRAM location. It's now possible to be done since the DW uMCTL2 DDRC driver supports the actual system address reported to the MCI core. The only thing left to do is to auto-detect the ECC Scrub feature availability and set the mem_ctl.info.scrub_mode mode with SCRUB_SW_SRC if the feature is unavailable. The rest will be done by the MCI core when the single-bit errors happen. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/edac/synopsys_edac.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index d5d82531719b..b36f7ec4a79e 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -32,6 +32,7 @@ #define SNPS_EDAC_MOD_VER "1" /* DDR capabilities */ +#define SNPS_CAP_ECC_SCRUB BIT(0) #define SNPS_CAP_ZYNQMP BIT(31) /* Synopsys uMCTL2 DDR controller registers that are relevant to ECC */ @@ -114,6 +115,7 @@ #define DDR_MSTR_MEM_LPDDR4 BIT(5) /* ECC CFG0 register definitions */ +#define ECC_CFG0_DIS_SCRUB BIT(4) #define ECC_CFG0_MODE_MASK GENMASK(2, 0) /* ECC status register definitions */ @@ -1008,6 +1010,10 @@ static int snps_get_ddrc_info(struct snps_edac_priv *priv) return -ENXIO; } + /* Assume HW-src scrub is always available if it isn't disabled */ + if (!(regval & ECC_CFG0_DIS_SCRUB)) + priv->info.caps |= SNPS_CAP_ECC_SCRUB; + /* Auto-detect the basic HIF/SDRAM bus parameters */ regval = readl(priv->baseaddr + DDR_MSTR_OFST); @@ -1484,8 +1490,14 @@ static struct mem_ctl_info *snps_mc_create(struct snps_edac_priv *priv) MEM_FLAG_DDR3 | MEM_FLAG_LPDDR3 | MEM_FLAG_DDR4 | MEM_FLAG_LPDDR4; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; - mci->scrub_cap = SCRUB_FLAG_HW_SRC; - mci->scrub_mode = SCRUB_NONE; + + if (priv->info.caps & SNPS_CAP_ECC_SCRUB) { + mci->scrub_mode = SCRUB_HW_SRC; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; + } else { + mci->scrub_mode = SCRUB_SW_SRC; + mci->scrub_cap = SCRUB_FLAG_SW_SRC; + } mci->edac_cap = EDAC_FLAG_SECDED; mci->ctl_name = "snps_umctl2_ddrc"; @@ -1578,6 +1590,8 @@ static int snps_ddrc_info_show(struct seq_file *s, void *data) seq_puts(s, "Caps:"); if (priv->info.caps) { + if (priv->info.caps & SNPS_CAP_ECC_SCRUB) + seq_puts(s, " +Scrub"); if (priv->info.caps & SNPS_CAP_ZYNQMP) seq_puts(s, " +ZynqMP"); } else { -- 2.37.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Serge Semin <Sergey.Semin@baikalelectronics.ru> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michal Simek <michal.simek@xilinx.com>, Borislav Petkov <bp@alien8.de>, Mauro Carvalho Chehab <mchehab@kernel.org>, Tony Luck <tony.luck@intel.com>, James Morse <james.morse@arm.com>, Robert Richter <rric@kernel.org> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>, Serge Semin <fancer.lancer@gmail.com>, Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>, Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>, Manish Narani <manish.narani@xilinx.com>, Dinh Nguyen <dinguyen@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v3 04/13] EDAC/synopsys: Add optional ECC Scrub support Date: Fri, 30 Sep 2022 02:41:12 +0300 [thread overview] Message-ID: <20220929234121.13955-5-Sergey.Semin@baikalelectronics.ru> (raw) In-Reply-To: <20220929234121.13955-1-Sergey.Semin@baikalelectronics.ru> DW uMCTL2 DDRC ECC has a so called ECC Scrub feature in case if an single-bit error is detected. The scrub is executed as a new RMW operation to the location that resulted in a single-bit error thus fixing the ECC code preserved in the SDRAM. But that feature not only optional, but also runtime switchable. So there can be platforms with DW uMCTL2 DDRC not supporting hardware-base scrub. In those cases the single-bit errors will still be detected but won't be fixed until the next SDRAM write commands to the erroneous location. Since the ECC Scrub feature availability is detectable by means of the ECCCFG0.dis_scrub flag state we can use it to tune the MCI core up so one would automatically execute the platform-specific the platform-specific scrubbing to the affected SDRAM location. It's now possible to be done since the DW uMCTL2 DDRC driver supports the actual system address reported to the MCI core. The only thing left to do is to auto-detect the ECC Scrub feature availability and set the mem_ctl.info.scrub_mode mode with SCRUB_SW_SRC if the feature is unavailable. The rest will be done by the MCI core when the single-bit errors happen. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/edac/synopsys_edac.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index d5d82531719b..b36f7ec4a79e 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -32,6 +32,7 @@ #define SNPS_EDAC_MOD_VER "1" /* DDR capabilities */ +#define SNPS_CAP_ECC_SCRUB BIT(0) #define SNPS_CAP_ZYNQMP BIT(31) /* Synopsys uMCTL2 DDR controller registers that are relevant to ECC */ @@ -114,6 +115,7 @@ #define DDR_MSTR_MEM_LPDDR4 BIT(5) /* ECC CFG0 register definitions */ +#define ECC_CFG0_DIS_SCRUB BIT(4) #define ECC_CFG0_MODE_MASK GENMASK(2, 0) /* ECC status register definitions */ @@ -1008,6 +1010,10 @@ static int snps_get_ddrc_info(struct snps_edac_priv *priv) return -ENXIO; } + /* Assume HW-src scrub is always available if it isn't disabled */ + if (!(regval & ECC_CFG0_DIS_SCRUB)) + priv->info.caps |= SNPS_CAP_ECC_SCRUB; + /* Auto-detect the basic HIF/SDRAM bus parameters */ regval = readl(priv->baseaddr + DDR_MSTR_OFST); @@ -1484,8 +1490,14 @@ static struct mem_ctl_info *snps_mc_create(struct snps_edac_priv *priv) MEM_FLAG_DDR3 | MEM_FLAG_LPDDR3 | MEM_FLAG_DDR4 | MEM_FLAG_LPDDR4; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; - mci->scrub_cap = SCRUB_FLAG_HW_SRC; - mci->scrub_mode = SCRUB_NONE; + + if (priv->info.caps & SNPS_CAP_ECC_SCRUB) { + mci->scrub_mode = SCRUB_HW_SRC; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; + } else { + mci->scrub_mode = SCRUB_SW_SRC; + mci->scrub_cap = SCRUB_FLAG_SW_SRC; + } mci->edac_cap = EDAC_FLAG_SECDED; mci->ctl_name = "snps_umctl2_ddrc"; @@ -1578,6 +1590,8 @@ static int snps_ddrc_info_show(struct seq_file *s, void *data) seq_puts(s, "Caps:"); if (priv->info.caps) { + if (priv->info.caps & SNPS_CAP_ECC_SCRUB) + seq_puts(s, " +Scrub"); if (priv->info.caps & SNPS_CAP_ZYNQMP) seq_puts(s, " +ZynqMP"); } else { -- 2.37.3
next prev parent reply other threads:[~2022-09-30 0:01 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-29 23:41 [PATCH v3 00/13] EDAC/synopsys: Add generic resources and Baikal-T1 support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 01/13] dt-bindings: memory: snps: Convert the schema to being generic Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-10-05 13:12 ` Rob Herring 2022-10-05 13:12 ` Rob Herring 2022-09-29 23:41 ` [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-10-03 13:24 ` Rob Herring 2022-10-03 13:24 ` Rob Herring 2022-10-05 14:59 ` Krzysztof Kozlowski 2022-10-05 14:59 ` Krzysztof Kozlowski 2022-10-06 12:26 ` Serge Semin 2022-10-06 12:26 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 03/13] EDAC/synopsys: Add multi-ranked memory support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` Serge Semin [this message] 2022-09-29 23:41 ` [PATCH v3 04/13] EDAC/synopsys: Add optional ECC Scrub support Serge Semin 2022-09-29 23:41 ` [PATCH v3 05/13] EDAC/synopsys: Drop ECC poison address from private data Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 06/13] EDAC/synopsys: Add data poisoning disable support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 07/13] EDAC/synopsys: Split up ECC UE/CE IRQs handler Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 08/13] EDAC/synopsys: Add individual named ECC IRQs support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 09/13] EDAC/synopsys: Add DFI alert_n IRQ support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 10/13] EDAC/synopsys: Add reference clocks support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 11/13] EDAC/synopsys: Add ECC Scrubber support Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 12/13] EDAC/synopsys: Drop vendor-specific arch dependency Serge Semin 2022-09-29 23:41 ` Serge Semin 2022-09-29 23:41 ` [PATCH v3 13/13] EDAC/synopsys: Add Baikal-T1 DDRC support Serge Semin 2022-09-29 23:41 ` Serge Semin
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