From: guoren@kernel.org
To: guoren@kernel.org, palmer@dabbelt.com, palmer@rivosinc.com,
heiko@sntech.de, arnd@arndb.de, songmuchun@bytedance.com,
catalin.marinas@arm.com, chenhuacai@loongson.cn,
Conor.Dooley@microchip.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu
Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-mm@kvack.org,
Guo Ren <guoren@linux.alibaba.com>, Will Deacon <will@kernel.org>,
Steven Price <steven.price@arm.com>
Subject: [PATCH 1/2] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte
Date: Sun, 23 Oct 2022 09:32:04 -0400 [thread overview]
Message-ID: <20221023133205.3493564-2-guoren@kernel.org> (raw)
In-Reply-To: <20221023133205.3493564-1-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
RISC-V follows the arm64 flush_icache_pte mechanism and also includes
its bug. The patch ensures that instructions are observable in a new
mapping. For more details, see 588a513d3425 ("arm64: Fix race condition
on PG_dcache_clean in __sync_icache_dcache()").
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Steven Price <steven.price@arm.com>
---
arch/riscv/mm/cacheflush.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..7c9f97fa3938 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -82,7 +82,9 @@ void flush_icache_pte(pte_t pte)
{
struct page *page = pte_page(pte);
- if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+ if (!test_bit(PG_dcache_clean, &page->flags)) {
flush_icache_all();
+ set_bit(PG_dcache_clean, &page->flags);
+ }
}
#endif /* CONFIG_MMU */
--
2.36.1
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org, palmer@dabbelt.com, palmer@rivosinc.com,
heiko@sntech.de, arnd@arndb.de, songmuchun@bytedance.com,
catalin.marinas@arm.com, chenhuacai@loongson.cn,
Conor.Dooley@microchip.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu
Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-mm@kvack.org,
Guo Ren <guoren@linux.alibaba.com>, Will Deacon <will@kernel.org>,
Steven Price <steven.price@arm.com>
Subject: [PATCH 1/2] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte
Date: Sun, 23 Oct 2022 09:32:04 -0400 [thread overview]
Message-ID: <20221023133205.3493564-2-guoren@kernel.org> (raw)
In-Reply-To: <20221023133205.3493564-1-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
RISC-V follows the arm64 flush_icache_pte mechanism and also includes
its bug. The patch ensures that instructions are observable in a new
mapping. For more details, see 588a513d3425 ("arm64: Fix race condition
on PG_dcache_clean in __sync_icache_dcache()").
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Steven Price <steven.price@arm.com>
---
arch/riscv/mm/cacheflush.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..7c9f97fa3938 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -82,7 +82,9 @@ void flush_icache_pte(pte_t pte)
{
struct page *page = pte_page(pte);
- if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+ if (!test_bit(PG_dcache_clean, &page->flags)) {
flush_icache_all();
+ set_bit(PG_dcache_clean, &page->flags);
+ }
}
#endif /* CONFIG_MMU */
--
2.36.1
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next prev parent reply other threads:[~2022-10-23 13:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-23 13:32 [PATCH 0/2] Enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP & fixup race condition on PG_dcache_clean guoren
2022-10-23 13:32 ` guoren
2022-10-23 13:32 ` guoren [this message]
2022-10-23 13:32 ` [PATCH 1/2] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte guoren
2022-10-23 13:32 ` [PATCH 2/2] riscv: Enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP guoren
2022-10-23 13:32 ` guoren
2022-10-24 7:07 ` Muchun Song
2022-10-24 7:07 ` Muchun Song
2022-10-24 8:02 ` Guo Ren
2022-10-24 8:02 ` Guo Ren
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