From: Suraj Kandpal <suraj.kandpal@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC
Date: Mon, 7 Nov 2022 14:16:27 +0530 [thread overview]
Message-ID: <20221107084634.1353266-2-suraj.kandpal@intel.com> (raw)
In-Reply-To: <20221107084634.1353266-1-suraj.kandpal@intel.com>
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Add helper function to check if the DP sink supports DSC with the given
output format.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
include/drm/display/drm_dp_helper.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index ab55453f2d2c..6c1706280746 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -193,6 +193,12 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
DP_DSC_SLICE_WIDTH_MULTIPLIER;
}
+/* Check if sink supports DSC with given output format */
+static inline bool
+drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
+{
+ return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
+}
/* Forward Error Correction Support on DP 1.4 */
static inline bool
--
2.25.1
next prev parent reply other threads:[~2022-11-07 8:48 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 15:26 [Intel-gfx] [PATCH v4 0/4] Enable YCbCr420 for VDSC Suraj Kandpal
2022-10-14 15:26 ` [Intel-gfx] [PATCH v4 1/4] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2022-10-14 15:26 ` [Intel-gfx] [PATCH v4 2/4] drm/i915: Adding the new registers for DSC Suraj Kandpal
2022-10-14 15:26 ` [Intel-gfx] [PATCH v4 3/4] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2022-10-14 15:26 ` [Intel-gfx] [PATCH v4 4/4] drm/i915: Fill in native_420 field Suraj Kandpal
2022-10-14 16:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC Patchwork
2022-10-14 16:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-14 16:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-14 17:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-17 4:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC (rev2) Patchwork
2022-10-17 5:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-17 13:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC (rev3) Patchwork
2022-10-17 13:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-17 15:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-18 0:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-19 15:41 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 2/8] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 3/8] drm/i915: Adding the new registers for DSC Suraj Kandpal
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 4/8] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 5/8] drm/i915: Fill in native_420 field Suraj Kandpal
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Suraj Kandpal
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs Suraj Kandpal
2022-11-07 7:26 ` [Intel-gfx] [PATCH v5 8/8] drm/i915: Code styling fixes Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 2/8] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 3/8] drm/i915: Adding the new registers for DSC Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 4/8] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 5/8] drm/i915: Fill in native_420 field Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs Suraj Kandpal
2022-11-07 7:34 ` [Intel-gfx] [PATCH v5 8/8] drm/i915: Code styling fixes Suraj Kandpal
2022-11-07 8:30 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable YCbCr420 for VDSC (rev3) Patchwork
2022-11-07 8:46 ` [Intel-gfx] [PATCH 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07 8:46 ` Suraj Kandpal [this message]
2022-11-07 8:46 ` [Intel-gfx] [PATCH 2/8] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2022-11-07 8:46 ` [Intel-gfx] [PATCH 3/8] drm/i915: Adding the new registers for DSC Suraj Kandpal
2022-11-07 8:46 ` [Intel-gfx] [PATCH 4/8] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07 8:46 ` [Intel-gfx] [PATCH 5/8] drm/i915: Fill in native_420 field Suraj Kandpal
2022-11-07 8:46 ` [Intel-gfx] [PATCH 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Suraj Kandpal
2022-11-07 8:46 ` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs Suraj Kandpal
2022-11-07 8:46 ` [Intel-gfx] [PATCH 8/8] drm/i915: Code styling fixes Suraj Kandpal
2022-10-28 11:19 [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC Swati Sharma
2022-10-28 11:19 ` [Intel-gfx] [PATCH 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC Swati Sharma
2022-11-07 8:42 [Intel-gfx] [PATCH 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07 8:42 ` [Intel-gfx] [PATCH 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
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