From: Carlo Caione <ccaione@baylibre.com>
To: Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>,
Mark Brown <broonie@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
David Airlie <airlied@gmail.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Kevin Hilman <khilman@baylibre.com>,
Daniel Vetter <daniel@ffwll.ch>
Cc: linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org,
Carlo Caione <ccaione@baylibre.com>
Subject: [PATCH 3/3] spi: meson-spicc: Lower CS between bursts
Date: Thu, 17 Nov 2022 09:47:41 +0100 [thread overview]
Message-ID: <20221116-s905x_spi_ili9486-v1-3-630401cb62d5@baylibre.com> (raw)
In-Reply-To: <20221116-s905x_spi_ili9486-v1-0-630401cb62d5@baylibre.com>
On some hardware (reproduced on S905X) when a large payload is
transmitted over SPI in bursts at the end of each burst, the clock line
briefly fluctuates creating spurious clock transitions that are being
recognised by the connected device as a genuine pulses, creating an
offset in the data being transmitted.
Lower the GPIO CS between bursts to avoid the clock being interpreted as
valid.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
drivers/spi/spi-meson-spicc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index d47f2623a60f..af8d74b53519 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -291,6 +291,10 @@ static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
static irqreturn_t meson_spicc_irq(int irq, void *data)
{
struct meson_spicc_device *spicc = (void *) data;
+ struct spi_device *spi_dev;
+
+ spi_dev = spicc->message->spi;
+ gpiod_set_value(spi_dev->cs_gpiod, 0);
writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
@@ -309,6 +313,8 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
/* Setup burst */
meson_spicc_setup_burst(spicc);
+ gpiod_set_value(spi_dev->cs_gpiod, 1);
+
/* Start burst */
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
--
b4 0.10.1
WARNING: multiple messages have this Message-ID (diff)
From: Carlo Caione <ccaione@baylibre.com>
To: Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>,
Mark Brown <broonie@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
David Airlie <airlied@gmail.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Kevin Hilman <khilman@baylibre.com>,
Daniel Vetter <daniel@ffwll.ch>
Cc: linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org,
Carlo Caione <ccaione@baylibre.com>
Subject: [PATCH 3/3] spi: meson-spicc: Lower CS between bursts
Date: Thu, 17 Nov 2022 09:47:41 +0100 [thread overview]
Message-ID: <20221116-s905x_spi_ili9486-v1-3-630401cb62d5@baylibre.com> (raw)
In-Reply-To: <20221116-s905x_spi_ili9486-v1-0-630401cb62d5@baylibre.com>
On some hardware (reproduced on S905X) when a large payload is
transmitted over SPI in bursts at the end of each burst, the clock line
briefly fluctuates creating spurious clock transitions that are being
recognised by the connected device as a genuine pulses, creating an
offset in the data being transmitted.
Lower the GPIO CS between bursts to avoid the clock being interpreted as
valid.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
drivers/spi/spi-meson-spicc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index d47f2623a60f..af8d74b53519 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -291,6 +291,10 @@ static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
static irqreturn_t meson_spicc_irq(int irq, void *data)
{
struct meson_spicc_device *spicc = (void *) data;
+ struct spi_device *spi_dev;
+
+ spi_dev = spicc->message->spi;
+ gpiod_set_value(spi_dev->cs_gpiod, 0);
writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
@@ -309,6 +313,8 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
/* Setup burst */
meson_spicc_setup_burst(spicc);
+ gpiod_set_value(spi_dev->cs_gpiod, 1);
+
/* Start burst */
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
--
b4 0.10.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Carlo Caione <ccaione@baylibre.com>
To: Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>,
Mark Brown <broonie@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
David Airlie <airlied@gmail.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Kevin Hilman <khilman@baylibre.com>,
Daniel Vetter <daniel@ffwll.ch>
Cc: linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org,
Carlo Caione <ccaione@baylibre.com>
Subject: [PATCH 3/3] spi: meson-spicc: Lower CS between bursts
Date: Thu, 17 Nov 2022 09:47:41 +0100 [thread overview]
Message-ID: <20221116-s905x_spi_ili9486-v1-3-630401cb62d5@baylibre.com> (raw)
In-Reply-To: <20221116-s905x_spi_ili9486-v1-0-630401cb62d5@baylibre.com>
On some hardware (reproduced on S905X) when a large payload is
transmitted over SPI in bursts at the end of each burst, the clock line
briefly fluctuates creating spurious clock transitions that are being
recognised by the connected device as a genuine pulses, creating an
offset in the data being transmitted.
Lower the GPIO CS between bursts to avoid the clock being interpreted as
valid.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
drivers/spi/spi-meson-spicc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index d47f2623a60f..af8d74b53519 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -291,6 +291,10 @@ static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
static irqreturn_t meson_spicc_irq(int irq, void *data)
{
struct meson_spicc_device *spicc = (void *) data;
+ struct spi_device *spi_dev;
+
+ spi_dev = spicc->message->spi;
+ gpiod_set_value(spi_dev->cs_gpiod, 0);
writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
@@ -309,6 +313,8 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
/* Setup burst */
meson_spicc_setup_burst(spicc);
+ gpiod_set_value(spi_dev->cs_gpiod, 1);
+
/* Start burst */
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
--
b4 0.10.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Carlo Caione <ccaione@baylibre.com>
To: Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>,
Mark Brown <broonie@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
David Airlie <airlied@gmail.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Kevin Hilman <khilman@baylibre.com>,
Daniel Vetter <daniel@ffwll.ch>
Cc: Carlo Caione <ccaione@baylibre.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] spi: meson-spicc: Lower CS between bursts
Date: Thu, 17 Nov 2022 09:47:41 +0100 [thread overview]
Message-ID: <20221116-s905x_spi_ili9486-v1-3-630401cb62d5@baylibre.com> (raw)
In-Reply-To: <20221116-s905x_spi_ili9486-v1-0-630401cb62d5@baylibre.com>
On some hardware (reproduced on S905X) when a large payload is
transmitted over SPI in bursts at the end of each burst, the clock line
briefly fluctuates creating spurious clock transitions that are being
recognised by the connected device as a genuine pulses, creating an
offset in the data being transmitted.
Lower the GPIO CS between bursts to avoid the clock being interpreted as
valid.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
drivers/spi/spi-meson-spicc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index d47f2623a60f..af8d74b53519 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -291,6 +291,10 @@ static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
static irqreturn_t meson_spicc_irq(int irq, void *data)
{
struct meson_spicc_device *spicc = (void *) data;
+ struct spi_device *spi_dev;
+
+ spi_dev = spicc->message->spi;
+ gpiod_set_value(spi_dev->cs_gpiod, 0);
writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
@@ -309,6 +313,8 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
/* Setup burst */
meson_spicc_setup_burst(spicc);
+ gpiod_set_value(spi_dev->cs_gpiod, 1);
+
/* Start burst */
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
--
b4 0.10.1
next prev parent reply other threads:[~2022-11-17 8:48 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-17 8:47 [PATCH 0/3] Fix SPICC and ILI9486 drivers Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` [PATCH 1/3] drm/tiny: rpi-lcd-35: Enable driver module autoloading Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` [PATCH 2/3] drm/tiny: ili9486: Do not assume 8-bit only SPI controllers Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 11:09 ` Mark Brown
2022-11-17 11:09 ` Mark Brown
2022-11-17 11:09 ` Mark Brown
2022-11-17 11:09 ` Mark Brown
2022-11-17 13:40 ` Carlo Caione
2022-11-17 13:40 ` Carlo Caione
2022-11-17 13:40 ` Carlo Caione
2022-11-17 13:40 ` Carlo Caione
2022-11-17 14:59 ` Mark Brown
2022-11-17 14:59 ` Mark Brown
2022-11-17 14:59 ` Mark Brown
2022-11-17 14:59 ` Mark Brown
2022-11-18 10:36 ` Carlo Caione
2022-11-18 10:36 ` Carlo Caione
2022-11-18 10:36 ` Carlo Caione
2022-11-18 10:36 ` Carlo Caione
2022-11-18 15:44 ` Mark Brown
2022-11-18 15:44 ` Mark Brown
2022-11-18 15:44 ` Mark Brown
2022-11-18 15:44 ` Mark Brown
2022-11-18 19:02 ` Carlo Caione
2022-11-18 19:02 ` Carlo Caione
2022-11-18 19:02 ` Carlo Caione
2022-11-18 19:02 ` Carlo Caione
2022-11-17 8:47 ` Carlo Caione [this message]
2022-11-17 8:47 ` [PATCH 3/3] spi: meson-spicc: Lower CS between bursts Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:47 ` Carlo Caione
2022-11-17 8:54 ` Neil Armstrong
2022-11-17 8:54 ` Neil Armstrong
2022-11-17 8:54 ` Neil Armstrong
2022-11-17 8:54 ` Neil Armstrong
2022-11-17 14:05 ` Carlo Caione
2022-11-17 14:05 ` Carlo Caione
2022-11-17 14:05 ` Carlo Caione
2022-11-17 14:05 ` Carlo Caione
2022-11-17 10:59 ` Mark Brown
2022-11-17 10:59 ` Mark Brown
2022-11-17 10:59 ` Mark Brown
2022-11-17 10:59 ` Mark Brown
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