From: Conor Dooley <conor.dooley@microchip.com> To: <linux-riscv@lists.infradead.org> Cc: Conor Dooley <conor.dooley@microchip.com>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com>, Guo Ren <guoren@kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Date: Thu, 24 Nov 2022 13:04:41 +0000 [thread overview] Message-ID: <20221124130440.306771-3-conor.dooley@microchip.com> (raw) In-Reply-To: <20221124130440.306771-1-conor.dooley@microchip.com> I used the wikipedia table for ordering extensions when updating the pattern here in foo. Unfortunately that table did not match canonical order, as defined by the RISC-V ISA Manual, which defines extension ordering in (what is currently) Table 41, "Standard ISA extension names". Fix things up by re-sorting v (vector) and adding p (packed-simd) & j (dynamic languages). The e (reduced integer) and g (general) extensions are still intentionally left out. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e80c967a4fa4..b7462ea2dbe4 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.38.1
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com> To: <linux-riscv@lists.infradead.org> Cc: Conor Dooley <conor.dooley@microchip.com>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com>, Guo Ren <guoren@kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Date: Thu, 24 Nov 2022 13:04:41 +0000 [thread overview] Message-ID: <20221124130440.306771-3-conor.dooley@microchip.com> (raw) In-Reply-To: <20221124130440.306771-1-conor.dooley@microchip.com> I used the wikipedia table for ordering extensions when updating the pattern here in foo. Unfortunately that table did not match canonical order, as defined by the RISC-V ISA Manual, which defines extension ordering in (what is currently) Table 41, "Standard ISA extension names". Fix things up by re-sorting v (vector) and adding p (packed-simd) & j (dynamic languages). The e (reduced integer) and g (general) extensions are still intentionally left out. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e80c967a4fa4..b7462ea2dbe4 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.38.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-24 13:08 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-24 13:04 [PATCH 0/2] riscv,isa fixups Conor Dooley 2022-11-24 13:04 ` Conor Dooley 2022-11-24 13:04 ` [PATCH 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions Conor Dooley 2022-11-24 13:04 ` Conor Dooley 2022-11-25 1:12 ` Guo Ren 2022-11-25 1:12 ` Guo Ren 2022-11-24 13:04 ` Conor Dooley [this message] 2022-11-24 13:04 ` [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Conor Dooley 2022-11-24 13:42 ` Heiko Stübner 2022-11-24 13:42 ` Heiko Stübner 2022-11-24 13:52 ` Conor Dooley 2022-11-24 13:52 ` Conor Dooley 2022-11-28 17:41 ` Palmer Dabbelt 2022-11-28 17:41 ` Palmer Dabbelt 2022-11-28 18:08 ` Conor Dooley 2022-11-28 18:08 ` Conor Dooley 2022-11-28 18:12 ` Palmer Dabbelt 2022-11-28 18:12 ` Palmer Dabbelt 2022-11-28 19:17 ` Conor Dooley 2022-11-28 19:17 ` Conor Dooley 2022-11-28 23:41 ` Palmer Dabbelt 2022-11-28 23:41 ` Palmer Dabbelt 2022-11-29 5:19 ` Andrew Jones 2022-11-29 5:19 ` Andrew Jones 2022-11-29 11:40 ` Conor Dooley 2022-11-29 11:40 ` Conor Dooley 2022-11-29 14:47 ` [RFC 0/2] Putting some basic order on isa extension stuff Conor Dooley 2022-11-29 14:47 ` Conor Dooley 2022-11-29 15:48 ` Andrew Jones 2022-11-29 15:48 ` Andrew Jones 2022-11-29 16:50 ` Conor Dooley 2022-11-29 16:50 ` Conor Dooley 2022-11-29 14:47 ` [RFC 1/2] RISC-V: clarify ISA string ordering rules in cpu.c Conor Dooley 2022-11-29 14:47 ` Conor Dooley 2022-11-29 16:12 ` Andrew Jones 2022-11-29 16:12 ` Andrew Jones 2022-11-29 16:54 ` Conor Dooley 2022-11-29 16:54 ` Conor Dooley 2022-11-29 17:19 ` Andrew Jones 2022-11-29 17:19 ` Andrew Jones 2022-11-29 17:48 ` Conor Dooley 2022-11-29 17:48 ` Conor Dooley 2022-11-29 14:47 ` [RFC 2/2] RISC-V: resort all extensions in "canonical" order Conor Dooley 2022-11-29 14:47 ` Conor Dooley 2022-11-29 16:35 ` Andrew Jones 2022-11-29 16:35 ` Andrew Jones 2022-12-01 13:51 ` [PATCH] Documentation: riscv: note that counter access is part of the uABI Conor Dooley 2022-12-01 13:51 ` Conor Dooley 2022-12-01 19:21 ` Palmer Dabbelt 2022-12-01 19:21 ` Palmer Dabbelt 2022-12-03 10:38 ` Jonathan Corbet 2022-12-03 10:38 ` Jonathan Corbet 2022-12-03 10:45 ` Jonathan Corbet 2022-12-03 10:45 ` Jonathan Corbet 2022-12-03 10:56 ` Conor Dooley 2022-12-03 10:56 ` Conor Dooley 2023-01-09 21:36 ` Atish Patra 2023-01-09 21:36 ` Atish Patra 2023-01-09 21:46 ` Conor Dooley 2023-01-09 21:46 ` Conor Dooley 2022-11-25 1:13 ` [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Guo Ren 2022-11-25 1:13 ` Guo Ren
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