From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>, dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com>, Vinay Belgaumkar <vinay.belgaumkar@intel.com>, John C Harrison <John.C.Harrison@intel.com> Subject: [PATCH v2 5/6] drm/i915/gsc: Disable GSC engine and power well if FW is not selected Date: Mon, 5 Dec 2022 17:19:07 -0800 [thread overview] Message-ID: <20221206011908.2745508-6-daniele.ceraolospurio@intel.com> (raw) In-Reply-To: <20221206011908.2745508-1-daniele.ceraolospurio@intel.com> From: Jonathan Cavitt <jonathan.cavitt@intel.com> The GSC CS is only used for communicating with the GSC FW, so no need to initialize it if we're not going to use the FW. If we're not using neither the engine nor the microcontoller, then we can also disable the power well. IMPORTANT: lack of GSC FW breaks media C6 due to opposing requirements between CS setup and forcewake idleness. See in-code comment for detail. Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: John C Harrison <John.C.Harrison@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/intel_uncore.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c33e0d72d670..99c4b866addd 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -894,6 +894,24 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) engine_mask_apply_compute_fuses(gt); engine_mask_apply_copy_fuses(gt); + /* + * The only use of the GSC CS is to load and communicate with the GSC + * FW, so we have no use for it if we don't have the FW. + * + * IMPORTANT: in cases where we don't have the GSC FW, we have a + * catch-22 situation that breaks media C6 due to 2 requirements: + * 1) once turned on, the GSC power well will not go to sleep unless the + * GSC FW is loaded. + * 2) to enable idling (which is required for media C6) we need to + * initialize the IDLE_MSG register for the GSC CS and do at least 1 + * submission, which will wake up the GSC power well. + */ + if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(>->uc)) { + drm_notice(>->i915->drm, + "No GSC FW selected, disabling GSC CS and media C6\n"); + info->engine_mask &= ~BIT(GSC0); + } + return info->engine_mask; } diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 3bfb4af0df78..cb45e4a4ace4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -2701,6 +2701,9 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, if (fw_domains & BIT(domain_id)) fw_domain_fini(uncore, domain_id); } + + if ((fw_domains & BIT(FW_DOMAIN_ID_GSC)) && !HAS_ENGINE(gt, GSC0)) + fw_domain_fini(uncore, FW_DOMAIN_ID_GSC); } /* -- 2.37.3
WARNING: multiple messages have this Message-ID (diff)
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>, dri-devel@lists.freedesktop.org, Rodrigo Vivi <rodrigo.vivi@intel.com> Subject: [Intel-gfx] [PATCH v2 5/6] drm/i915/gsc: Disable GSC engine and power well if FW is not selected Date: Mon, 5 Dec 2022 17:19:07 -0800 [thread overview] Message-ID: <20221206011908.2745508-6-daniele.ceraolospurio@intel.com> (raw) In-Reply-To: <20221206011908.2745508-1-daniele.ceraolospurio@intel.com> From: Jonathan Cavitt <jonathan.cavitt@intel.com> The GSC CS is only used for communicating with the GSC FW, so no need to initialize it if we're not going to use the FW. If we're not using neither the engine nor the microcontoller, then we can also disable the power well. IMPORTANT: lack of GSC FW breaks media C6 due to opposing requirements between CS setup and forcewake idleness. See in-code comment for detail. Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: John C Harrison <John.C.Harrison@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/intel_uncore.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c33e0d72d670..99c4b866addd 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -894,6 +894,24 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) engine_mask_apply_compute_fuses(gt); engine_mask_apply_copy_fuses(gt); + /* + * The only use of the GSC CS is to load and communicate with the GSC + * FW, so we have no use for it if we don't have the FW. + * + * IMPORTANT: in cases where we don't have the GSC FW, we have a + * catch-22 situation that breaks media C6 due to 2 requirements: + * 1) once turned on, the GSC power well will not go to sleep unless the + * GSC FW is loaded. + * 2) to enable idling (which is required for media C6) we need to + * initialize the IDLE_MSG register for the GSC CS and do at least 1 + * submission, which will wake up the GSC power well. + */ + if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(>->uc)) { + drm_notice(>->i915->drm, + "No GSC FW selected, disabling GSC CS and media C6\n"); + info->engine_mask &= ~BIT(GSC0); + } + return info->engine_mask; } diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 3bfb4af0df78..cb45e4a4ace4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -2701,6 +2701,9 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, if (fw_domains & BIT(domain_id)) fw_domain_fini(uncore, domain_id); } + + if ((fw_domains & BIT(FW_DOMAIN_ID_GSC)) && !HAS_ENGINE(gt, GSC0)) + fw_domain_fini(uncore, FW_DOMAIN_ID_GSC); } /* -- 2.37.3
next prev parent reply other threads:[~2022-12-06 1:16 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-06 1:19 [PATCH v2 0/6] drm/i915: Add support for GSC FW loading Daniele Ceraolo Spurio 2022-12-06 1:19 ` [Intel-gfx] " Daniele Ceraolo Spurio 2022-12-06 1:19 ` [PATCH v2 1/6] drm/i915/uc: Introduce GSC FW Daniele Ceraolo Spurio 2022-12-06 1:19 ` [Intel-gfx] " Daniele Ceraolo Spurio 2022-12-08 4:09 ` Teres Alexis, Alan Previn 2022-12-08 4:09 ` [Intel-gfx] " Teres Alexis, Alan Previn 2022-12-06 1:19 ` [PATCH v2 2/6] drm/i915/gsc: Skip the version check when fetching the " Daniele Ceraolo Spurio 2022-12-06 1:19 ` [Intel-gfx] " Daniele Ceraolo Spurio 2022-12-08 5:23 ` Teres Alexis, Alan Previn 2022-12-08 5:23 ` [Intel-gfx] " Teres Alexis, Alan Previn 2022-12-06 1:19 ` [PATCH v2 3/6] drm/i915/gsc: GSC firmware loading Daniele Ceraolo Spurio 2022-12-06 1:19 ` [Intel-gfx] " Daniele Ceraolo Spurio 2022-12-06 5:15 ` [PATCH] " Daniele Ceraolo Spurio 2022-12-06 5:15 ` [Intel-gfx] " Daniele Ceraolo Spurio 2022-12-07 10:16 ` Teres Alexis, Alan Previn 2022-12-07 10:16 ` [Intel-gfx] " Teres Alexis, Alan Previn 2022-12-07 16:46 ` Ceraolo Spurio, Daniele 2022-12-07 16:46 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-12-06 5:39 ` [Intel-gfx] [PATCH v2 3/6] " kernel test robot 2022-12-06 5:49 ` kernel test robot 2022-12-06 12:03 ` kernel test robot 2022-12-06 1:19 ` [PATCH v2 4/6] drm/i915/gsc: Do a driver-FLR on unload if GSC was loaded Daniele Ceraolo Spurio 2022-12-06 1:19 ` [Intel-gfx] " Daniele Ceraolo Spurio 2022-12-06 8:52 ` Rodrigo Vivi 2022-12-06 1:19 ` Daniele Ceraolo Spurio [this message] 2022-12-06 1:19 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/gsc: Disable GSC engine and power well if FW is not selected Daniele Ceraolo Spurio 2022-12-06 1:19 ` [PATCH v2 6/6] drm/i915/mtl: MTL has one GSC CS on the media GT Daniele Ceraolo Spurio 2022-12-06 1:19 ` [Intel-gfx] " Daniele Ceraolo Spurio 2022-12-06 2:41 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Add support for GSC FW loading (rev2) Patchwork 2022-12-06 5:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for GSC FW loading (rev3) Patchwork 2022-12-06 5:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-12-06 5:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-12-06 7:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20221206011908.2745508-6-daniele.ceraolospurio@intel.com \ --to=daniele.ceraolospurio@intel.com \ --cc=John.C.Harrison@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=jonathan.cavitt@intel.com \ --cc=rodrigo.vivi@intel.com \ --cc=vinay.belgaumkar@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.