From: Florian Fainelli <f.fainelli@gmail.com> To: linux-kernel@vger.kernel.org Cc: Florian Fainelli <f.fainelli@gmail.com>, Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh@kernel.org>, Doug Berger <opendmb@gmail.com>, Jason Cooper <jason@lakedaemon.net>, linux-mips@vger.kernel.org (open list:BROADCOM BMIPS MIPS ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH 1/2] irqchip/irq-brcmstb-l2: Set IRQ_LEVEL for level triggered interrupts Date: Fri, 16 Dec 2022 15:09:33 -0800 [thread overview] Message-ID: <20221216230934.2478345-2-f.fainelli@gmail.com> (raw) In-Reply-To: <20221216230934.2478345-1-f.fainelli@gmail.com> When support for the level triggered interrupt controller flavor was added with c0ca7262088e, we forgot to update the flags to be set to contain IRQ_LEVEL. While the flow handler is correct, the output from /proc/interrupts does not show such interrupts as being level triggered when they are, correct that. Fixes: c0ca7262088e ("irqchip/brcmstb-l2: Add support for the BCM7271 L2 controller") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- drivers/irqchip/irq-brcmstb-l2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c index e4efc08ac594..091b0fe7e324 100644 --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c @@ -161,6 +161,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, *init_params) { unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + unsigned int set = 0; struct brcmstb_l2_intc_data *data; struct irq_chip_type *ct; int ret; @@ -208,9 +209,12 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) flags |= IRQ_GC_BE_IO; + if (init_params->handler == handle_level_irq) + set |= IRQ_LEVEL; + /* Allocate a single Generic IRQ chip for this node */ ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, - np->full_name, init_params->handler, clr, 0, flags); + np->full_name, init_params->handler, clr, set, flags); if (ret) { pr_err("failed to allocate generic irq chip\n"); goto out_free_domain; -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Florian Fainelli <f.fainelli@gmail.com> To: linux-kernel@vger.kernel.org Cc: Florian Fainelli <f.fainelli@gmail.com>, Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh@kernel.org>, Doug Berger <opendmb@gmail.com>, Jason Cooper <jason@lakedaemon.net>, linux-mips@vger.kernel.org (open list:BROADCOM BMIPS MIPS ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH 1/2] irqchip/irq-brcmstb-l2: Set IRQ_LEVEL for level triggered interrupts Date: Fri, 16 Dec 2022 15:09:33 -0800 [thread overview] Message-ID: <20221216230934.2478345-2-f.fainelli@gmail.com> (raw) In-Reply-To: <20221216230934.2478345-1-f.fainelli@gmail.com> When support for the level triggered interrupt controller flavor was added with c0ca7262088e, we forgot to update the flags to be set to contain IRQ_LEVEL. While the flow handler is correct, the output from /proc/interrupts does not show such interrupts as being level triggered when they are, correct that. Fixes: c0ca7262088e ("irqchip/brcmstb-l2: Add support for the BCM7271 L2 controller") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- drivers/irqchip/irq-brcmstb-l2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c index e4efc08ac594..091b0fe7e324 100644 --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c @@ -161,6 +161,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, *init_params) { unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + unsigned int set = 0; struct brcmstb_l2_intc_data *data; struct irq_chip_type *ct; int ret; @@ -208,9 +209,12 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) flags |= IRQ_GC_BE_IO; + if (init_params->handler == handle_level_irq) + set |= IRQ_LEVEL; + /* Allocate a single Generic IRQ chip for this node */ ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, - np->full_name, init_params->handler, clr, 0, flags); + np->full_name, init_params->handler, clr, set, flags); if (ret) { pr_err("failed to allocate generic irq chip\n"); goto out_free_domain; -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-12-16 23:10 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-16 23:09 [PATCH 0/2] Couple of Broadcom L2 driver fixes Florian Fainelli 2022-12-16 23:09 ` Florian Fainelli 2022-12-16 23:09 ` Florian Fainelli [this message] 2022-12-16 23:09 ` [PATCH 1/2] irqchip/irq-brcmstb-l2: Set IRQ_LEVEL for level triggered interrupts Florian Fainelli 2023-02-18 14:28 ` [irqchip: irq/irqchip-next] " irqchip-bot for Florian Fainelli 2022-12-16 23:09 ` [PATCH 2/2] irqchip/irq-bcm7120-l2: " Florian Fainelli 2022-12-16 23:09 ` Florian Fainelli 2023-02-18 14:28 ` [irqchip: irq/irqchip-next] " irqchip-bot for Florian Fainelli 2022-12-17 18:25 ` [PATCH 0/2] Couple of Broadcom L2 driver fixes Philippe Mathieu-Daudé 2022-12-17 18:25 ` Philippe Mathieu-Daudé 2023-01-26 0:10 ` Florian Fainelli 2023-01-26 0:10 ` Florian Fainelli 2023-02-14 23:23 ` Florian Fainelli 2023-02-14 23:23 ` Florian Fainelli
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