From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() where possible Date: Fri, 23 Dec 2022 10:42:47 +0100 [thread overview] Message-ID: <20221223094259.87373-12-angelogioacchino.delregno@collabora.com> (raw) In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> mtk_clk_simple_probe() is a function that registers mtk gate clocks and, if reset data is present, a reset controller and across all of the MTK clock drivers, such a function is duplicated many times: switch to the common mtk_clk_simple_probe() function for all of the clock drivers that are registering as platform drivers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/clk/mediatek/clk-mt2701-aud.c | 26 +++---- drivers/clk/mediatek/clk-mt2701-eth.c | 34 +++------ drivers/clk/mediatek/clk-mt2701-g3d.c | 56 +++----------- drivers/clk/mediatek/clk-mt2701-hif.c | 36 +++------ drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++------------- drivers/clk/mediatek/clk-mt6779.c | 42 ++++++----- drivers/clk/mediatek/clk-mt7622-aud.c | 49 +++---------- drivers/clk/mediatek/clk-mt7622-eth.c | 82 ++++----------------- drivers/clk/mediatek/clk-mt7622-hif.c | 85 ++++----------------- drivers/clk/mediatek/clk-mt7629-hif.c | 85 ++++----------------- drivers/clk/mediatek/clk-mt8183-audio.c | 19 +++-- drivers/clk/mediatek/clk-mt8183.c | 75 ++++++++----------- drivers/clk/mediatek/clk-mt8192-aud.c | 25 +++---- drivers/clk/mediatek/clk-mt8192.c | 98 ++++++++----------------- 14 files changed, 236 insertions(+), 559 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c index ab13ab618fb5..1fd6d96b34dc 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -76,6 +76,7 @@ static const struct mtk_gate_regs audio3_cg_regs = { }; static const struct mtk_gate audio_clks[] = { + GATE_DUMMY(CLK_DUMMY, "aud_dummy"), /* AUDIO0 */ GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), @@ -138,29 +139,26 @@ static const struct mtk_gate audio_clks[] = { GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), }; +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + static const struct of_device_id of_match_clk_mt2701_aud[] = { - { .compatible = "mediatek,mt2701-audsys", }, - {} + { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc }, + { /* sentinel */ } }; static int clk_mt2701_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUD_NR); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - goto err_clk_provider; + return r; } r = devm_of_platform_populate(&pdev->dev); @@ -170,13 +168,13 @@ static int clk_mt2701_aud_probe(struct platform_device *pdev) return 0; err_plat_populate: - of_clk_del_provider(node); -err_clk_provider: + mtk_clk_simple_remove(pdev); return r; } static struct platform_driver clk_mt2701_aud_drv = { .probe = clk_mt2701_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-aud", .of_match_table = of_match_clk_mt2701_aud, diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 9670e1e170f2..bd3fddf53ce1 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -26,6 +26,7 @@ static const struct mtk_gate_regs eth_cg_regs = { } static const struct mtk_gate eth_clks[] = { + GATE_DUMMY(CLK_DUMMY, "eth_dummy"), GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), @@ -44,35 +45,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; +static const struct mtk_clk_desc eth_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(eth_clks), + .rst_desc = &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt2701_eth[] = { - { .compatible = "mediatek,mt2701-ethsys", }, + { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc }, {} }; -static int clk_mt2701_eth_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - static struct platform_driver clk_mt2701_eth_drv = { - .probe = clk_mt2701_eth_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-eth", .of_match_table = of_match_clk_mt2701_eth, diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 11391b144267..499a170ba5f9 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -32,6 +32,7 @@ static const struct mtk_gate_regs g3d_cg_regs = { }; static const struct mtk_gate g3d_clks[] = { + GATE_DUMMY(CLK_DUMMY, "g3d_dummy"), GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; @@ -43,57 +44,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt2701_g3dsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); - - mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} +static const struct mtk_clk_desc g3d_desc = { + .clks = g3d_clks, + .num_clks = ARRAY_SIZE(g3d_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt2701_g3d[] = { - { - .compatible = "mediatek,mt2701-g3dsys", - .data = clk_mt2701_g3dsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc }, + { /* sentinel */ } }; -static int clk_mt2701_g3d_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt2701_g3d_drv = { - .probe = clk_mt2701_g3d_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-g3d", .of_match_table = of_match_clk_mt2701_g3d, diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index c14c0bb10f88..5d113838b3e4 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -26,6 +26,7 @@ static const struct mtk_gate_regs hif_cg_regs = { } static const struct mtk_gate hif_clks[] = { + GATE_DUMMY(CLK_DUMMY, "hif_dummy"), GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21), GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22), GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24), @@ -41,37 +42,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; +static const struct mtk_clk_desc hif_desc = { + .clks = hif_clks, + .num_clks = ARRAY_SIZE(hif_clks), + .rst_desc = &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt2701_hif[] = { - { .compatible = "mediatek,mt2701-hifsys", }, + { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc }, {} }; -static int clk_mt2701_hif_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); - - mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - return r; - } - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return 0; -} - static struct platform_driver clk_mt2701_hif_drv = { - .probe = clk_mt2701_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-hif", .of_match_table = of_match_clk_mt2701_hif, diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 5cadcf6ca9b7..c4bee791f570 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1362,50 +1362,6 @@ static int clk_mt2712_top_probe(struct platform_device *pdev) return r; } -static int clk_mt2712_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); - - return r; -} - -static int clk_mt2712_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); - - return r; -} - static int clk_mt2712_mcu_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1440,12 +1396,6 @@ static const struct of_device_id of_match_clk_mt2712[] = { }, { .compatible = "mediatek,mt2712-topckgen", .data = clk_mt2712_top_probe, - }, { - .compatible = "mediatek,mt2712-infracfg", - .data = clk_mt2712_infra_probe, - }, { - .compatible = "mediatek,mt2712-pericfg", - .data = clk_mt2712_peri_probe, }, { .compatible = "mediatek,mt2712-mcucfg", .data = clk_mt2712_mcu_probe, @@ -1472,6 +1422,33 @@ static int clk_mt2712_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc[0], +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), + .rst_desc = &clk_rst_desc[1], +}; + +static const struct of_device_id of_match_clk_mt2712_simple[] = { + { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt2712_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt2712-simple", + .of_match_table = of_match_clk_mt2712_simple, + }, +}; + static struct platform_driver clk_mt2712_drv = { .probe = clk_mt2712_probe, .driver = { @@ -1482,7 +1459,11 @@ static struct platform_driver clk_mt2712_drv = { static int __init clk_mt2712_init(void) { - return platform_driver_register(&clk_mt2712_drv); + int ret = platform_driver_register(&clk_mt2712_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt2712_simple_drv); } arch_initcall(clk_mt2712_init); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 6d1fb19be77b..479fb38766ea 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -880,6 +880,7 @@ static const struct mtk_gate_regs infra3_cg_regs = { &mtk_clk_gate_ops_setclr) static const struct mtk_gate infra_clks[] = { + GATE_DUMMY(CLK_DUMMY, "ifa_dummy"), /* INFRA0 */ GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), @@ -1256,19 +1257,6 @@ static int clk_mt6779_top_probe(struct platform_device *pdev) return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } -static int clk_mt6779_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static const struct of_device_id of_match_clk_mt6779[] = { { .compatible = "mediatek,mt6779-apmixed", @@ -1276,9 +1264,6 @@ static const struct of_device_id of_match_clk_mt6779[] = { }, { .compatible = "mediatek,mt6779-topckgen", .data = clk_mt6779_top_probe, - }, { - .compatible = "mediatek,mt6779-infracfg_ao", - .data = clk_mt6779_infra_probe, }, { /* sentinel */ } @@ -1302,6 +1287,25 @@ static int clk_mt6779_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), +}; + +static const struct of_device_id of_match_clk_mt6779_infra[] = { + { .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6779_infra_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6779-infra", + .of_match_table = of_match_clk_mt6779_infra, + }, +}; + static struct platform_driver clk_mt6779_drv = { .probe = clk_mt6779_probe, .driver = { @@ -1312,7 +1316,11 @@ static struct platform_driver clk_mt6779_drv = { static int __init clk_mt6779_init(void) { - return platform_driver_register(&clk_mt6779_drv); + int ret = platform_driver_register(&clk_mt6779_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt6779_infra_drv); } arch_initcall(clk_mt6779_init); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c index d0379d8704af..86464cc750e2 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -130,24 +130,21 @@ static const struct mtk_gate audio_clks[] = { GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), }; -static int clk_mt7622_audiosys_init(struct platform_device *pdev) +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + +static int clk_mt7622_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - goto err_clk_provider; + return r; } r = devm_of_platform_populate(&pdev->dev); @@ -157,40 +154,18 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) return 0; err_plat_populate: - of_clk_del_provider(node); -err_clk_provider: + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt7622_aud[] = { - { - .compatible = "mediatek,mt7622-audsys", - .data = clk_mt7622_audiosys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, + { /* sentinel */ } }; -static int clk_mt7622_aud_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_aud_drv = { .probe = clk_mt7622_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-aud", .of_match_table = of_match_clk_mt7622_aud, diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 9b4a26ca0f44..7dd0cec802f7 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -73,80 +73,26 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7622_ethsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); - - mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); +static const struct mtk_clk_desc eth_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(eth_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc sgmii_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(sgmii_clks), +}; static const struct of_device_id of_match_clk_mt7622_eth[] = { - { - .compatible = "mediatek,mt7622-ethsys", - .data = clk_mt7622_ethsys_init, - }, { - .compatible = "mediatek,mt7622-sgmiisys", - .data = clk_mt7622_sgmiisys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, + { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, + { /* sentinel */ } }; -static int clk_mt7622_eth_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_eth_drv = { - .probe = clk_mt7622_eth_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-eth", .of_match_table = of_match_clk_mt7622_eth, diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 8cf37f75ca77..ab5cad0c2b1c 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -84,82 +84,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7622_pciesys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +static const struct mtk_clk_desc ssusb_desc = { + .clks = ssusb_clks, + .num_clks = ARRAY_SIZE(ssusb_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc pcie_desc = { + .clks = pcie_clks, + .num_clks = ARRAY_SIZE(pcie_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt7622_hif[] = { - { - .compatible = "mediatek,mt7622-pciesys", - .data = clk_mt7622_pciesys_init, - }, { - .compatible = "mediatek,mt7622-ssusbsys", - .data = clk_mt7622_ssusbsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, + { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, + { /* sentinel */ } }; -static int clk_mt7622_hif_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_hif_drv = { - .probe = clk_mt7622_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-hif", .of_match_table = of_match_clk_mt7622_hif, diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 44fbd88b4647..c3eb09ea6036 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -79,82 +79,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7629_pciesys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +static const struct mtk_clk_desc ssusb_desc = { + .clks = ssusb_clks, + .num_clks = ARRAY_SIZE(ssusb_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc pcie_desc = { + .clks = pcie_clks, + .num_clks = ARRAY_SIZE(pcie_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt7629_hif[] = { - { - .compatible = "mediatek,mt7629-pciesys", - .data = clk_mt7629_pciesys_init, - }, { - .compatible = "mediatek,mt7629-ssusbsys", - .data = clk_mt7629_ssusbsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc }, + { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, + { /* sentinel */ } }; -static int clk_mt7629_hif_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7629_hif_drv = { - .probe = clk_mt7629_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7629-hif", .of_match_table = of_match_clk_mt7629_hif, diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c index f4c6448b6f74..f5600450b4d1 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -67,35 +67,34 @@ static const struct mtk_gate audio_clks[] = { 20), }; +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + static int clk_mt8183_audio_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) return r; r = devm_of_platform_populate(&pdev->dev); if (r) - of_clk_del_provider(node); + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt8183_audio[] = { - { .compatible = "mediatek,mt8183-audiosys", }, + { .compatible = "mediatek,mt8183-audiosys", .data = &audio_desc }, {} }; static struct platform_driver clk_mt8183_audio_drv = { .probe = clk_mt8183_audio_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8183-audio", .of_match_table = of_match_clk_mt8183_audio, diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 10a82b542376..f1d84c0730d5 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1187,43 +1187,6 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) top_clk_data); } -static int clk_mt8183_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, - "%s(): could not register clock provider: %d\n", - __func__, r); - return r; - } - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt8183_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static int clk_mt8183_mcu_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1249,12 +1212,6 @@ static const struct of_device_id of_match_clk_mt8183[] = { }, { .compatible = "mediatek,mt8183-topckgen", .data = clk_mt8183_top_probe, - }, { - .compatible = "mediatek,mt8183-infracfg", - .data = clk_mt8183_infra_probe, - }, { - .compatible = "mediatek,mt8183-pericfg", - .data = clk_mt8183_peri_probe, }, { .compatible = "mediatek,mt8183-mcucfg", .data = clk_mt8183_mcu_probe, @@ -1281,6 +1238,32 @@ static int clk_mt8183_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc, +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), +}; + +static const struct of_device_id of_match_clk_mt8183_simple[] = { + { .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8183_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8183-simple", + .of_match_table = of_match_clk_mt8183_simple, + }, +}; + static struct platform_driver clk_mt8183_drv = { .probe = clk_mt8183_probe, .driver = { @@ -1291,7 +1274,11 @@ static struct platform_driver clk_mt8183_drv = { static int __init clk_mt8183_init(void) { - return platform_driver_register(&clk_mt8183_drv); + int ret = platform_driver_register(&clk_mt8183_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt8183_simple_drv); } arch_initcall(clk_mt8183_init); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c index 3acadca2452a..d52f671e20ce 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -77,39 +77,34 @@ static const struct mtk_gate aud_clks[] = { GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4), }; +static const struct mtk_clk_desc aud_desc = { + .clks = aud_clks, + .num_clks = ARRAY_SIZE(aud_clks), +}; + static int clk_mt8192_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), - clk_data, &pdev->dev); - if (r) - return r; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) return r; r = devm_of_platform_populate(&pdev->dev); if (r) - of_clk_del_provider(node); + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt8192_aud[] = { - { .compatible = "mediatek,mt8192-audsys", }, - {} + { .compatible = "mediatek,mt8192-audsys", .data = &aud_desc }, + { /* sentinel */ } }; static struct platform_driver clk_mt8192_aud_drv = { .probe = clk_mt8192_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8192-aud", .of_match_table = of_match_clk_mt8192_aud, diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 3ca068a4c552..9a9d51bfb84d 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1158,66 +1158,6 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) return r; } -static int clk_mt8192_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - if (r) - goto unregister_gates; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8192_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(peri_clks, ARRAY_SIZE(peri_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1255,12 +1195,6 @@ static const struct of_device_id of_match_clk_mt8192[] = { }, { .compatible = "mediatek,mt8192-topckgen", .data = clk_mt8192_top_probe, - }, { - .compatible = "mediatek,mt8192-infracfg", - .data = clk_mt8192_infra_probe, - }, { - .compatible = "mediatek,mt8192-pericfg", - .data = clk_mt8192_peri_probe, }, { /* sentinel */ } @@ -1282,6 +1216,32 @@ static int clk_mt8192_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc, +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_simple[] = { + { .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8192_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8192-simple", + .of_match_table = of_match_clk_mt8192_simple, + }, +}; + static struct platform_driver clk_mt8192_drv = { .probe = clk_mt8192_probe, .driver = { @@ -1292,7 +1252,11 @@ static struct platform_driver clk_mt8192_drv = { static int __init clk_mt8192_init(void) { - return platform_driver_register(&clk_mt8192_drv); + int ret = platform_driver_register(&clk_mt8192_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt8192_simple_drv); } arch_initcall(clk_mt8192_init); -- 2.39.0
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() where possible Date: Fri, 23 Dec 2022 10:42:47 +0100 [thread overview] Message-ID: <20221223094259.87373-12-angelogioacchino.delregno@collabora.com> (raw) In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> mtk_clk_simple_probe() is a function that registers mtk gate clocks and, if reset data is present, a reset controller and across all of the MTK clock drivers, such a function is duplicated many times: switch to the common mtk_clk_simple_probe() function for all of the clock drivers that are registering as platform drivers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/clk/mediatek/clk-mt2701-aud.c | 26 +++---- drivers/clk/mediatek/clk-mt2701-eth.c | 34 +++------ drivers/clk/mediatek/clk-mt2701-g3d.c | 56 +++----------- drivers/clk/mediatek/clk-mt2701-hif.c | 36 +++------ drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++------------- drivers/clk/mediatek/clk-mt6779.c | 42 ++++++----- drivers/clk/mediatek/clk-mt7622-aud.c | 49 +++---------- drivers/clk/mediatek/clk-mt7622-eth.c | 82 ++++----------------- drivers/clk/mediatek/clk-mt7622-hif.c | 85 ++++----------------- drivers/clk/mediatek/clk-mt7629-hif.c | 85 ++++----------------- drivers/clk/mediatek/clk-mt8183-audio.c | 19 +++-- drivers/clk/mediatek/clk-mt8183.c | 75 ++++++++----------- drivers/clk/mediatek/clk-mt8192-aud.c | 25 +++---- drivers/clk/mediatek/clk-mt8192.c | 98 ++++++++----------------- 14 files changed, 236 insertions(+), 559 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c index ab13ab618fb5..1fd6d96b34dc 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -76,6 +76,7 @@ static const struct mtk_gate_regs audio3_cg_regs = { }; static const struct mtk_gate audio_clks[] = { + GATE_DUMMY(CLK_DUMMY, "aud_dummy"), /* AUDIO0 */ GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), @@ -138,29 +139,26 @@ static const struct mtk_gate audio_clks[] = { GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), }; +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + static const struct of_device_id of_match_clk_mt2701_aud[] = { - { .compatible = "mediatek,mt2701-audsys", }, - {} + { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc }, + { /* sentinel */ } }; static int clk_mt2701_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUD_NR); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - goto err_clk_provider; + return r; } r = devm_of_platform_populate(&pdev->dev); @@ -170,13 +168,13 @@ static int clk_mt2701_aud_probe(struct platform_device *pdev) return 0; err_plat_populate: - of_clk_del_provider(node); -err_clk_provider: + mtk_clk_simple_remove(pdev); return r; } static struct platform_driver clk_mt2701_aud_drv = { .probe = clk_mt2701_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-aud", .of_match_table = of_match_clk_mt2701_aud, diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 9670e1e170f2..bd3fddf53ce1 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -26,6 +26,7 @@ static const struct mtk_gate_regs eth_cg_regs = { } static const struct mtk_gate eth_clks[] = { + GATE_DUMMY(CLK_DUMMY, "eth_dummy"), GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), @@ -44,35 +45,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; +static const struct mtk_clk_desc eth_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(eth_clks), + .rst_desc = &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt2701_eth[] = { - { .compatible = "mediatek,mt2701-ethsys", }, + { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc }, {} }; -static int clk_mt2701_eth_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - static struct platform_driver clk_mt2701_eth_drv = { - .probe = clk_mt2701_eth_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-eth", .of_match_table = of_match_clk_mt2701_eth, diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 11391b144267..499a170ba5f9 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -32,6 +32,7 @@ static const struct mtk_gate_regs g3d_cg_regs = { }; static const struct mtk_gate g3d_clks[] = { + GATE_DUMMY(CLK_DUMMY, "g3d_dummy"), GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; @@ -43,57 +44,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt2701_g3dsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); - - mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} +static const struct mtk_clk_desc g3d_desc = { + .clks = g3d_clks, + .num_clks = ARRAY_SIZE(g3d_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt2701_g3d[] = { - { - .compatible = "mediatek,mt2701-g3dsys", - .data = clk_mt2701_g3dsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc }, + { /* sentinel */ } }; -static int clk_mt2701_g3d_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt2701_g3d_drv = { - .probe = clk_mt2701_g3d_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-g3d", .of_match_table = of_match_clk_mt2701_g3d, diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index c14c0bb10f88..5d113838b3e4 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -26,6 +26,7 @@ static const struct mtk_gate_regs hif_cg_regs = { } static const struct mtk_gate hif_clks[] = { + GATE_DUMMY(CLK_DUMMY, "hif_dummy"), GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21), GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22), GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24), @@ -41,37 +42,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; +static const struct mtk_clk_desc hif_desc = { + .clks = hif_clks, + .num_clks = ARRAY_SIZE(hif_clks), + .rst_desc = &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt2701_hif[] = { - { .compatible = "mediatek,mt2701-hifsys", }, + { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc }, {} }; -static int clk_mt2701_hif_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); - - mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - return r; - } - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return 0; -} - static struct platform_driver clk_mt2701_hif_drv = { - .probe = clk_mt2701_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-hif", .of_match_table = of_match_clk_mt2701_hif, diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 5cadcf6ca9b7..c4bee791f570 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1362,50 +1362,6 @@ static int clk_mt2712_top_probe(struct platform_device *pdev) return r; } -static int clk_mt2712_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); - - return r; -} - -static int clk_mt2712_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); - - return r; -} - static int clk_mt2712_mcu_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1440,12 +1396,6 @@ static const struct of_device_id of_match_clk_mt2712[] = { }, { .compatible = "mediatek,mt2712-topckgen", .data = clk_mt2712_top_probe, - }, { - .compatible = "mediatek,mt2712-infracfg", - .data = clk_mt2712_infra_probe, - }, { - .compatible = "mediatek,mt2712-pericfg", - .data = clk_mt2712_peri_probe, }, { .compatible = "mediatek,mt2712-mcucfg", .data = clk_mt2712_mcu_probe, @@ -1472,6 +1422,33 @@ static int clk_mt2712_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc[0], +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), + .rst_desc = &clk_rst_desc[1], +}; + +static const struct of_device_id of_match_clk_mt2712_simple[] = { + { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt2712_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt2712-simple", + .of_match_table = of_match_clk_mt2712_simple, + }, +}; + static struct platform_driver clk_mt2712_drv = { .probe = clk_mt2712_probe, .driver = { @@ -1482,7 +1459,11 @@ static struct platform_driver clk_mt2712_drv = { static int __init clk_mt2712_init(void) { - return platform_driver_register(&clk_mt2712_drv); + int ret = platform_driver_register(&clk_mt2712_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt2712_simple_drv); } arch_initcall(clk_mt2712_init); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 6d1fb19be77b..479fb38766ea 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -880,6 +880,7 @@ static const struct mtk_gate_regs infra3_cg_regs = { &mtk_clk_gate_ops_setclr) static const struct mtk_gate infra_clks[] = { + GATE_DUMMY(CLK_DUMMY, "ifa_dummy"), /* INFRA0 */ GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), @@ -1256,19 +1257,6 @@ static int clk_mt6779_top_probe(struct platform_device *pdev) return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } -static int clk_mt6779_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static const struct of_device_id of_match_clk_mt6779[] = { { .compatible = "mediatek,mt6779-apmixed", @@ -1276,9 +1264,6 @@ static const struct of_device_id of_match_clk_mt6779[] = { }, { .compatible = "mediatek,mt6779-topckgen", .data = clk_mt6779_top_probe, - }, { - .compatible = "mediatek,mt6779-infracfg_ao", - .data = clk_mt6779_infra_probe, }, { /* sentinel */ } @@ -1302,6 +1287,25 @@ static int clk_mt6779_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), +}; + +static const struct of_device_id of_match_clk_mt6779_infra[] = { + { .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6779_infra_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6779-infra", + .of_match_table = of_match_clk_mt6779_infra, + }, +}; + static struct platform_driver clk_mt6779_drv = { .probe = clk_mt6779_probe, .driver = { @@ -1312,7 +1316,11 @@ static struct platform_driver clk_mt6779_drv = { static int __init clk_mt6779_init(void) { - return platform_driver_register(&clk_mt6779_drv); + int ret = platform_driver_register(&clk_mt6779_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt6779_infra_drv); } arch_initcall(clk_mt6779_init); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c index d0379d8704af..86464cc750e2 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -130,24 +130,21 @@ static const struct mtk_gate audio_clks[] = { GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), }; -static int clk_mt7622_audiosys_init(struct platform_device *pdev) +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + +static int clk_mt7622_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - goto err_clk_provider; + return r; } r = devm_of_platform_populate(&pdev->dev); @@ -157,40 +154,18 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) return 0; err_plat_populate: - of_clk_del_provider(node); -err_clk_provider: + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt7622_aud[] = { - { - .compatible = "mediatek,mt7622-audsys", - .data = clk_mt7622_audiosys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, + { /* sentinel */ } }; -static int clk_mt7622_aud_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_aud_drv = { .probe = clk_mt7622_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-aud", .of_match_table = of_match_clk_mt7622_aud, diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 9b4a26ca0f44..7dd0cec802f7 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -73,80 +73,26 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7622_ethsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); - - mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); +static const struct mtk_clk_desc eth_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(eth_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc sgmii_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(sgmii_clks), +}; static const struct of_device_id of_match_clk_mt7622_eth[] = { - { - .compatible = "mediatek,mt7622-ethsys", - .data = clk_mt7622_ethsys_init, - }, { - .compatible = "mediatek,mt7622-sgmiisys", - .data = clk_mt7622_sgmiisys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, + { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, + { /* sentinel */ } }; -static int clk_mt7622_eth_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_eth_drv = { - .probe = clk_mt7622_eth_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-eth", .of_match_table = of_match_clk_mt7622_eth, diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 8cf37f75ca77..ab5cad0c2b1c 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -84,82 +84,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7622_pciesys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +static const struct mtk_clk_desc ssusb_desc = { + .clks = ssusb_clks, + .num_clks = ARRAY_SIZE(ssusb_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc pcie_desc = { + .clks = pcie_clks, + .num_clks = ARRAY_SIZE(pcie_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt7622_hif[] = { - { - .compatible = "mediatek,mt7622-pciesys", - .data = clk_mt7622_pciesys_init, - }, { - .compatible = "mediatek,mt7622-ssusbsys", - .data = clk_mt7622_ssusbsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, + { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, + { /* sentinel */ } }; -static int clk_mt7622_hif_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_hif_drv = { - .probe = clk_mt7622_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-hif", .of_match_table = of_match_clk_mt7622_hif, diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 44fbd88b4647..c3eb09ea6036 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -79,82 +79,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7629_pciesys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +static const struct mtk_clk_desc ssusb_desc = { + .clks = ssusb_clks, + .num_clks = ARRAY_SIZE(ssusb_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc pcie_desc = { + .clks = pcie_clks, + .num_clks = ARRAY_SIZE(pcie_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt7629_hif[] = { - { - .compatible = "mediatek,mt7629-pciesys", - .data = clk_mt7629_pciesys_init, - }, { - .compatible = "mediatek,mt7629-ssusbsys", - .data = clk_mt7629_ssusbsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc }, + { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, + { /* sentinel */ } }; -static int clk_mt7629_hif_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7629_hif_drv = { - .probe = clk_mt7629_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7629-hif", .of_match_table = of_match_clk_mt7629_hif, diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c index f4c6448b6f74..f5600450b4d1 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -67,35 +67,34 @@ static const struct mtk_gate audio_clks[] = { 20), }; +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + static int clk_mt8183_audio_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) return r; r = devm_of_platform_populate(&pdev->dev); if (r) - of_clk_del_provider(node); + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt8183_audio[] = { - { .compatible = "mediatek,mt8183-audiosys", }, + { .compatible = "mediatek,mt8183-audiosys", .data = &audio_desc }, {} }; static struct platform_driver clk_mt8183_audio_drv = { .probe = clk_mt8183_audio_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8183-audio", .of_match_table = of_match_clk_mt8183_audio, diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 10a82b542376..f1d84c0730d5 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1187,43 +1187,6 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) top_clk_data); } -static int clk_mt8183_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, - "%s(): could not register clock provider: %d\n", - __func__, r); - return r; - } - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt8183_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static int clk_mt8183_mcu_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1249,12 +1212,6 @@ static const struct of_device_id of_match_clk_mt8183[] = { }, { .compatible = "mediatek,mt8183-topckgen", .data = clk_mt8183_top_probe, - }, { - .compatible = "mediatek,mt8183-infracfg", - .data = clk_mt8183_infra_probe, - }, { - .compatible = "mediatek,mt8183-pericfg", - .data = clk_mt8183_peri_probe, }, { .compatible = "mediatek,mt8183-mcucfg", .data = clk_mt8183_mcu_probe, @@ -1281,6 +1238,32 @@ static int clk_mt8183_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc, +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), +}; + +static const struct of_device_id of_match_clk_mt8183_simple[] = { + { .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8183_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8183-simple", + .of_match_table = of_match_clk_mt8183_simple, + }, +}; + static struct platform_driver clk_mt8183_drv = { .probe = clk_mt8183_probe, .driver = { @@ -1291,7 +1274,11 @@ static struct platform_driver clk_mt8183_drv = { static int __init clk_mt8183_init(void) { - return platform_driver_register(&clk_mt8183_drv); + int ret = platform_driver_register(&clk_mt8183_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt8183_simple_drv); } arch_initcall(clk_mt8183_init); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c index 3acadca2452a..d52f671e20ce 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -77,39 +77,34 @@ static const struct mtk_gate aud_clks[] = { GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4), }; +static const struct mtk_clk_desc aud_desc = { + .clks = aud_clks, + .num_clks = ARRAY_SIZE(aud_clks), +}; + static int clk_mt8192_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), - clk_data, &pdev->dev); - if (r) - return r; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) return r; r = devm_of_platform_populate(&pdev->dev); if (r) - of_clk_del_provider(node); + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt8192_aud[] = { - { .compatible = "mediatek,mt8192-audsys", }, - {} + { .compatible = "mediatek,mt8192-audsys", .data = &aud_desc }, + { /* sentinel */ } }; static struct platform_driver clk_mt8192_aud_drv = { .probe = clk_mt8192_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8192-aud", .of_match_table = of_match_clk_mt8192_aud, diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 3ca068a4c552..9a9d51bfb84d 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1158,66 +1158,6 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) return r; } -static int clk_mt8192_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - if (r) - goto unregister_gates; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8192_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(peri_clks, ARRAY_SIZE(peri_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1255,12 +1195,6 @@ static const struct of_device_id of_match_clk_mt8192[] = { }, { .compatible = "mediatek,mt8192-topckgen", .data = clk_mt8192_top_probe, - }, { - .compatible = "mediatek,mt8192-infracfg", - .data = clk_mt8192_infra_probe, - }, { - .compatible = "mediatek,mt8192-pericfg", - .data = clk_mt8192_peri_probe, }, { /* sentinel */ } @@ -1282,6 +1216,32 @@ static int clk_mt8192_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc, +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_simple[] = { + { .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8192_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8192-simple", + .of_match_table = of_match_clk_mt8192_simple, + }, +}; + static struct platform_driver clk_mt8192_drv = { .probe = clk_mt8192_probe, .driver = { @@ -1292,7 +1252,11 @@ static struct platform_driver clk_mt8192_drv = { static int __init clk_mt8192_init(void) { - return platform_driver_register(&clk_mt8192_drv); + int ret = platform_driver_register(&clk_mt8192_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt8192_simple_drv); } arch_initcall(clk_mt8192_init); -- 2.39.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-12-23 9:44 UTC|newest] Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-23 9:42 [PATCH v2 00/23] MediaTek clocks cleanups and improvements AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-23 9:42 ` [PATCH v2 01/23] clk: mediatek: mt8192: Correctly unregister and free clocks on failure AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-26 6:55 ` Chen-Yu Tsai 2022-12-26 6:55 ` Chen-Yu Tsai 2023-01-04 10:55 ` Markus Schneider-Pargmann 2023-01-04 10:55 ` Markus Schneider-Pargmann 2022-12-23 9:42 ` [PATCH v2 02/23] clk: mediatek: mt8192: Propagate struct device for gate clocks AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-26 6:56 ` Chen-Yu Tsai 2022-12-26 6:56 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 03/23] clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates() AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-26 7:05 ` Chen-Yu Tsai 2022-12-26 7:05 ` Chen-Yu Tsai 2023-01-04 11:21 ` Markus Schneider-Pargmann 2023-01-04 11:21 ` Markus Schneider-Pargmann 2023-01-10 11:05 ` AngeloGioacchino Del Regno 2023-01-10 11:05 ` AngeloGioacchino Del Regno 2022-12-23 9:42 ` [PATCH v2 04/23] clk: mediatek: cpumux: Propagate struct device where possible AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-26 7:07 ` Chen-Yu Tsai 2022-12-26 7:07 ` Chen-Yu Tsai 2023-01-06 17:00 ` Markus Schneider-Pargmann 2023-01-06 17:00 ` Markus Schneider-Pargmann 2022-12-23 9:42 ` [PATCH v2 05/23] clk: mediatek: clk-mtk: Propagate struct device for composites AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 4:37 ` Chen-Yu Tsai 2022-12-30 4:37 ` Chen-Yu Tsai 2023-01-06 17:09 ` Markus Schneider-Pargmann 2023-01-06 17:09 ` Markus Schneider-Pargmann 2022-12-23 9:42 ` [PATCH v2 06/23] clk: mediatek: clk-mux: Propagate struct device for mtk-mux AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 4:43 ` Chen-Yu Tsai 2022-12-30 4:43 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 07/23] clk: mediatek: clk-mtk: Add dummy clock ops AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-28 7:24 ` Miles Chen 2022-12-28 7:24 ` Miles Chen 2022-12-30 5:19 ` Chen-Yu Tsai 2022-12-30 5:19 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 08/23] clk: mediatek: mt8173: Migrate to platform driver and common probe AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 8:22 ` Chen-Yu Tsai 2022-12-30 8:22 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 09/23] clk: mediatek: mt8173: Remove mtk_clk_enable_critical() AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 4:58 ` Chen-Yu Tsai 2022-12-30 4:58 ` Chen-Yu Tsai 2023-01-10 12:32 ` AngeloGioacchino Del Regno 2023-01-10 12:32 ` AngeloGioacchino Del Regno 2023-01-11 2:27 ` Chen-Yu Tsai 2023-01-11 2:27 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 10/23] clk: mediatek: mt8173: Break down clock drivers and allow module build AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-24 1:47 ` kernel test robot 2022-12-23 9:42 ` AngeloGioacchino Del Regno [this message] 2022-12-23 9:42 ` [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() where possible AngeloGioacchino Del Regno 2022-12-28 7:50 ` Miles Chen 2022-12-28 7:50 ` Miles Chen 2022-12-30 5:12 ` Chen-Yu Tsai 2022-12-30 5:12 ` Chen-Yu Tsai 2023-01-10 13:31 ` AngeloGioacchino Del Regno 2023-01-10 13:31 ` AngeloGioacchino Del Regno 2023-01-11 2:47 ` Chen-Yu Tsai 2023-01-11 2:47 ` Chen-Yu Tsai 2023-01-11 8:56 ` [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() Miles Chen 2023-01-11 8:56 ` Miles Chen 2023-01-11 10:36 ` AngeloGioacchino Del Regno 2023-01-11 10:36 ` AngeloGioacchino Del Regno 2022-12-23 9:42 ` [PATCH v2 12/23] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-27 16:22 ` Miles Chen 2022-12-27 16:22 ` Miles Chen 2022-12-30 7:14 ` Chen-Yu Tsai 2022-12-30 7:14 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 13/23] clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe() AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-28 7:54 ` Miles Chen 2022-12-28 7:54 ` Miles Chen 2022-12-30 7:15 ` Chen-Yu Tsai 2022-12-30 7:15 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 14/23] clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-28 7:58 ` Miles Chen 2022-12-28 7:58 ` Miles Chen 2022-12-30 5:17 ` Chen-Yu Tsai 2022-12-30 5:17 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 15/23] clk: mediatek: mt8192: Join top_adj_divs and top_muxes AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-28 8:31 ` Miles Chen 2022-12-28 8:31 ` Miles Chen 2022-12-30 8:09 ` Chen-Yu Tsai 2022-12-30 8:09 ` Chen-Yu Tsai 2022-12-30 8:06 ` Chen-Yu Tsai 2022-12-30 8:06 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 16/23] clk: mediatek: mt8186: Join top_adj_div " AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 8:17 ` Chen-Yu Tsai 2022-12-30 8:17 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 17/23] clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 8:19 ` Chen-Yu Tsai 2022-12-30 8:19 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 18/23] clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe() AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-29 8:21 ` Miles Chen 2022-12-29 8:21 ` Miles Chen 2022-12-30 8:12 ` Chen-Yu Tsai 2022-12-30 8:12 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 19/23] clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 8:18 ` Chen-Yu Tsai 2022-12-30 8:18 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 20/23] clk: mediatek: clk-mt8186-topckgen: Migrate " AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 5:55 ` Miles Chen 2022-12-30 5:55 ` Miles Chen 2022-12-30 8:15 ` Chen-Yu Tsai 2022-12-30 8:15 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 21/23] clk: mediatek: clk-mt6795-topckgen: " AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 5:56 ` Miles Chen 2022-12-30 5:56 ` Miles Chen 2022-12-30 8:13 ` Chen-Yu Tsai 2022-12-30 8:13 ` Chen-Yu Tsai 2022-12-23 9:42 ` [PATCH v2 22/23] clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-30 5:23 ` Chen-Yu Tsai 2022-12-30 5:23 ` Chen-Yu Tsai 2022-12-30 6:04 ` Miles Chen 2022-12-30 6:04 ` Miles Chen 2022-12-23 9:42 ` [PATCH v2 23/23] clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() AngeloGioacchino Del Regno 2022-12-23 9:42 ` AngeloGioacchino Del Regno 2022-12-27 16:18 ` [PATCH v2 12/23] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() Miles Chen 2022-12-27 16:18 ` Miles Chen 2022-12-27 16:26 ` Miles Chen 2022-12-27 16:26 ` Miles Chen 2022-12-30 6:05 ` [PATCH v2 23/23] clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() Miles Chen 2022-12-30 6:05 ` Miles Chen 2022-12-30 8:14 ` Chen-Yu Tsai 2022-12-30 8:14 ` Chen-Yu Tsai 2022-12-30 6:13 ` [PATCH v2 00/23] MediaTek clocks cleanups and improvements Miles Chen 2022-12-30 6:13 ` Miles Chen 2022-12-30 6:42 ` Chen-Yu Tsai 2022-12-30 6:42 ` Chen-Yu Tsai 2022-12-30 7:19 ` Miles Chen 2022-12-30 7:19 ` Miles Chen 2023-01-03 9:36 ` Chen-Yu Tsai 2023-01-03 9:36 ` Chen-Yu Tsai 2022-12-23 20:33 [PATCH v2 10/23] clk: mediatek: mt8173: Break down clock drivers and allow module build kernel test robot 2022-12-24 7:13 ` Dan Carpenter 2022-12-24 7:13 ` Dan Carpenter
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