From: <daire.mcnamara@microchip.com> To: <conor.dooley@microchip.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <lpieralisi@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org> Cc: Daire McNamara <daire.mcnamara@microchip.com> Subject: [PATCH v3 05/11] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs Date: Wed, 11 Jan 2023 12:53:17 +0000 [thread overview] Message-ID: <20230111125323.1911373-6-daire.mcnamara@microchip.com> (raw) In-Reply-To: <20230111125323.1911373-1-daire.mcnamara@microchip.com> From: Daire McNamara <daire.mcnamara@microchip.com> Minor re-organisation so that event handlers can access both a pointer to the bridge area of the PCIe Root Port and the ctrl area of the PCIe Root Port. Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- drivers/pci/controller/pcie-microchip-host.c | 31 ++++++++++---------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 2efd48ef79d8..444ba99b070b 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -654,9 +654,10 @@ static inline u32 reg_to_event(u32 reg, struct event_map field) return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; } -static u32 pcie_events(void __iomem *addr) +static u32 pcie_events(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT); u32 val = 0; int i; @@ -666,9 +667,10 @@ static u32 pcie_events(void __iomem *addr) return val; } -static u32 sec_errors(void __iomem *addr) +static u32 sec_errors(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT); u32 val = 0; int i; @@ -678,9 +680,10 @@ static u32 sec_errors(void __iomem *addr) return val; } -static u32 ded_errors(void __iomem *addr) +static u32 ded_errors(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT); u32 val = 0; int i; @@ -690,9 +693,10 @@ static u32 ded_errors(void __iomem *addr) return val; } -static u32 local_events(void __iomem *addr) +static u32 local_events(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); u32 val = 0; int i; @@ -704,15 +708,12 @@ static u32 local_events(void __iomem *addr) static u32 get_events(struct mc_pcie *port) { - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; - void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; u32 events = 0; - events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT); - events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT); - events |= ded_errors(ctrl_base_addr + DED_ERROR_INT); - events |= local_events(bridge_base_addr + ISTATUS_LOCAL); + events |= pcie_events(port); + events |= sec_errors(port); + events |= ded_errors(port); + events |= local_events(port); return events; } -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: <daire.mcnamara@microchip.com> To: <conor.dooley@microchip.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <lpieralisi@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org> Cc: Daire McNamara <daire.mcnamara@microchip.com> Subject: [PATCH v3 05/11] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs Date: Wed, 11 Jan 2023 12:53:17 +0000 [thread overview] Message-ID: <20230111125323.1911373-6-daire.mcnamara@microchip.com> (raw) In-Reply-To: <20230111125323.1911373-1-daire.mcnamara@microchip.com> From: Daire McNamara <daire.mcnamara@microchip.com> Minor re-organisation so that event handlers can access both a pointer to the bridge area of the PCIe Root Port and the ctrl area of the PCIe Root Port. Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- drivers/pci/controller/pcie-microchip-host.c | 31 ++++++++++---------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 2efd48ef79d8..444ba99b070b 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -654,9 +654,10 @@ static inline u32 reg_to_event(u32 reg, struct event_map field) return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; } -static u32 pcie_events(void __iomem *addr) +static u32 pcie_events(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT); u32 val = 0; int i; @@ -666,9 +667,10 @@ static u32 pcie_events(void __iomem *addr) return val; } -static u32 sec_errors(void __iomem *addr) +static u32 sec_errors(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT); u32 val = 0; int i; @@ -678,9 +680,10 @@ static u32 sec_errors(void __iomem *addr) return val; } -static u32 ded_errors(void __iomem *addr) +static u32 ded_errors(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; + u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT); u32 val = 0; int i; @@ -690,9 +693,10 @@ static u32 ded_errors(void __iomem *addr) return val; } -static u32 local_events(void __iomem *addr) +static u32 local_events(struct mc_pcie *port) { - u32 reg = readl_relaxed(addr); + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); u32 val = 0; int i; @@ -704,15 +708,12 @@ static u32 local_events(void __iomem *addr) static u32 get_events(struct mc_pcie *port) { - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; - void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; u32 events = 0; - events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT); - events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT); - events |= ded_errors(ctrl_base_addr + DED_ERROR_INT); - events |= local_events(bridge_base_addr + ISTATUS_LOCAL); + events |= pcie_events(port); + events |= sec_errors(port); + events |= ded_errors(port); + events |= local_events(port); return events; } -- 2.25.1
next prev parent reply other threads:[~2023-01-11 12:53 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-11 12:53 [PATCH v3 00/11] PCI: microchip: Partition address translations daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-01-11 12:53 ` [PATCH v3 01/11] PCI: microchip: Correct the DED and SEC interrupt bit offsets daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-01-11 12:53 ` [PATCH v3 02/11] PCI: microchip: Remove cast warning for devm_add_action_or_reset() arg daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-01-11 18:18 ` Conor Dooley 2023-01-11 18:18 ` Conor Dooley 2023-01-11 12:53 ` [PATCH v3 03/11] PCI: microchip: enable building this driver as a module daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-01-11 17:25 ` Uwe Kleine-König 2023-01-11 17:25 ` Uwe Kleine-König 2023-01-11 18:20 ` Conor Dooley 2023-01-11 18:20 ` Conor Dooley 2023-01-11 12:53 ` [PATCH v3 04/11] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara [this message] 2023-01-11 12:53 ` [PATCH v3 05/11] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara 2023-01-11 12:53 ` [PATCH v3 06/11] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-01-11 12:53 ` [PATCH v3 07/11] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-02-02 11:45 ` Lorenzo Pieralisi 2023-02-02 11:45 ` Lorenzo Pieralisi 2023-01-11 12:53 ` [PATCH v3 08/11] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-01-11 12:53 ` [PATCH v3 09/11] PCI: microchip: Partition outbound address translation daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-02-02 11:28 ` Lorenzo Pieralisi 2023-02-02 11:28 ` Lorenzo Pieralisi 2023-01-11 12:53 ` [PATCH v3 10/11] PCI: microchip: Partition inbound " daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-02-02 11:31 ` Lorenzo Pieralisi 2023-02-02 11:31 ` Lorenzo Pieralisi 2023-02-02 12:13 ` Robin Murphy 2023-02-02 12:13 ` Robin Murphy 2023-01-11 12:53 ` [PATCH v3 11/11] riscv: dts: microchip: add parent ranges and dma-ranges for IKRD v2022.09 daire.mcnamara 2023-01-11 12:53 ` daire.mcnamara 2023-01-20 11:07 ` [PATCH v3 00/11] PCI: microchip: Partition address translations Conor Dooley 2023-01-20 11:07 ` Conor Dooley 2023-01-31 17:03 ` Daire.McNamara 2023-01-31 17:03 ` Daire.McNamara 2023-02-02 11:02 ` Lorenzo Pieralisi 2023-02-02 11:02 ` Lorenzo Pieralisi
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