From: Arun R Murthy <arun.r.murthy@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
jani.nikula@intel.com
Cc: Arun R Murthy <arun.r.murthy@intel.com>
Subject: [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Date: Fri, 20 Jan 2023 11:46:00 +0530 [thread overview]
Message-ID: <20230120061600.1451088-3-arun.r.murthy@intel.com> (raw)
In-Reply-To: <20230120061600.1451088-1-arun.r.murthy@intel.com>
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..7064e465423b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (intel_dp_is_uhbr(crtc_state) && passed)
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for Display version 13.
+ * Default value of bit 31 is '0' hence discarding the write
+ */
+ /* TODO: Corrective actions on SDP corruption yet to be defined */
}
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Arun R Murthy <arun.r.murthy@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
jani.nikula@intel.com
Subject: [Intel-gfx] [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
Date: Fri, 20 Jan 2023 11:46:00 +0530 [thread overview]
Message-ID: <20230120061600.1451088-3-arun.r.murthy@intel.com> (raw)
In-Reply-To: <20230120061600.1451088-1-arun.r.murthy@intel.com>
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..7064e465423b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (intel_dp_is_uhbr(crtc_state) && passed)
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for Display version 13.
+ * Default value of bit 31 is '0' hence discarding the write
+ */
+ /* TODO: Corrective actions on SDP corruption yet to be defined */
}
--
2.25.1
next prev parent reply other threads:[~2023-01-20 6:22 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 6:15 [PATCHv2 0/2] DP2.0 SDP CRC16 for 128/132b link layer Arun R Murthy
2023-01-20 6:15 ` [Intel-gfx] " Arun R Murthy
2023-01-20 6:15 ` [RESEND PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register Arun R Murthy
2023-01-20 6:15 ` [Intel-gfx] " Arun R Murthy
2023-01-20 6:16 ` Arun R Murthy [this message]
2023-01-20 6:16 ` [Intel-gfx] [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer Arun R Murthy
2023-01-26 15:00 ` Jani Nikula
2023-01-26 15:00 ` [Intel-gfx] " Jani Nikula
2023-01-20 6:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for DP2.0 SDP CRC16 for 128/132b " Patchwork
2023-01-20 7:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-02-07 5:26 ` [PATCHv3 0/2] " Arun R Murthy
2023-02-07 5:26 ` [Intel-gfx] " Arun R Murthy
2023-02-07 5:26 ` [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register Arun R Murthy
2023-02-07 5:26 ` [Intel-gfx] " Arun R Murthy
2023-02-07 5:26 ` [PATCHv3 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer Arun R Murthy
2023-02-07 5:26 ` [Intel-gfx] " Arun R Murthy
2023-02-14 9:27 ` Jani Nikula
2023-02-14 9:27 ` [Intel-gfx] " Jani Nikula
2023-02-14 9:28 ` Jani Nikula
2023-02-14 9:28 ` [Intel-gfx] " Jani Nikula
-- strict thread matches above, loose matches on Subject: below --
2023-02-14 9:34 [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b " Arun R Murthy
2023-02-14 9:34 ` [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b " Arun R Murthy
2023-02-27 9:56 ` Jani Nikula
2023-01-13 4:36 [PATCH 1/2] drm: Add SDP Error Detection Configuration Register Arun R Murthy
2023-01-20 5:59 ` [PATCHv2 " Arun R Murthy
2023-01-20 5:59 ` [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer Arun R Murthy
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