From: Conor Dooley <conor.dooley@microchip.com>
To: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 1/7] mailbox: mpfs: fix an incorrect mask width
Date: Fri, 20 Jan 2023 14:37:29 +0000 [thread overview]
Message-ID: <20230120143734.3438755-2-conor.dooley@microchip.com> (raw)
In-Reply-To: <20230120143734.3438755-1-conor.dooley@microchip.com>
The system controller registers on PolarFire SoC are 32 bits wide, so
16 + 16 as the first input to GENMASK_ULL() gives a 33 bit wide mask.
It probably should have been immediately obvious when it was pointed
out during review that the width required using GENMASK_ULL() - but I
scarcely knew what I was doing at the time and missed it.
The mistake ends up being moot as it is a mask after all, but it is
incorrect and should be fixed.
No functional change intended.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/mailbox/mailbox-mpfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
index 853901acaeec..d37560e91116 100644
--- a/drivers/mailbox/mailbox-mpfs.c
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -39,7 +39,7 @@
#define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY)
#define SCB_CTRL_POS (16)
-#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS)
+#define SCB_CTRL_MASK GENMASK(SCB_CTRL_POS + SCB_MASK_WIDTH - 1, SCB_CTRL_POS)
/* SCBCTRL service status register */
@@ -118,6 +118,7 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
}
opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu));
+
tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK;
writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
--
2.39.0
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 1/7] mailbox: mpfs: fix an incorrect mask width
Date: Fri, 20 Jan 2023 14:37:29 +0000 [thread overview]
Message-ID: <20230120143734.3438755-2-conor.dooley@microchip.com> (raw)
In-Reply-To: <20230120143734.3438755-1-conor.dooley@microchip.com>
The system controller registers on PolarFire SoC are 32 bits wide, so
16 + 16 as the first input to GENMASK_ULL() gives a 33 bit wide mask.
It probably should have been immediately obvious when it was pointed
out during review that the width required using GENMASK_ULL() - but I
scarcely knew what I was doing at the time and missed it.
The mistake ends up being moot as it is a mask after all, but it is
incorrect and should be fixed.
No functional change intended.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/mailbox/mailbox-mpfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
index 853901acaeec..d37560e91116 100644
--- a/drivers/mailbox/mailbox-mpfs.c
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -39,7 +39,7 @@
#define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY)
#define SCB_CTRL_POS (16)
-#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS)
+#define SCB_CTRL_MASK GENMASK(SCB_CTRL_POS + SCB_MASK_WIDTH - 1, SCB_CTRL_POS)
/* SCBCTRL service status register */
@@ -118,6 +118,7 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
}
opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu));
+
tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK;
writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
--
2.39.0
next prev parent reply other threads:[~2023-01-20 14:39 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 14:37 [PATCH v2 0/7] MPFS system controller/mailbox fixes Conor Dooley
2023-01-20 14:37 ` Conor Dooley
2023-01-20 14:37 ` Conor Dooley [this message]
2023-01-20 14:37 ` [PATCH v2 1/7] mailbox: mpfs: fix an incorrect mask width Conor Dooley
2023-01-20 14:37 ` [PATCH v2 2/7] mailbox: mpfs: switch to txdone_poll Conor Dooley
2023-01-20 14:37 ` Conor Dooley
2023-01-20 14:37 ` [PATCH v2 3/7] mailbox: mpfs: ditch a useless busy check Conor Dooley
2023-01-20 14:37 ` Conor Dooley
2023-01-20 14:37 ` [PATCH v2 4/7] soc: microchip: mpfs: fix some horrible alignment Conor Dooley
2023-01-20 14:37 ` Conor Dooley
2023-01-20 14:37 ` [PATCH v2 5/7] soc: microchip: mpfs: use a consistent completion timeout Conor Dooley
2023-01-20 14:37 ` Conor Dooley
2023-01-20 14:37 ` [PATCH v2 6/7] soc: microchip: mpfs: simplify error handling in mpfs_blocking_transaction() Conor Dooley
2023-01-20 14:37 ` Conor Dooley
2023-01-20 14:37 ` [PATCH v2 7/7] soc: microchip: mpfs: handle timeouts and failed services differently Conor Dooley
2023-01-20 14:37 ` Conor Dooley
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