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From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-renesas-soc@vger.kernel.org,
	Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
	Kieran Bingham <kieran.bingham@ideasonboard.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Subject: [PATCH v3.1 4/7] drm: rcar-du: lvds: Fix stop sequence
Date: Tue, 24 Jan 2023 00:50:13 +0200	[thread overview]
Message-ID: <20230123225013.10476-1-laurent.pinchart+renesas@ideasonboard.com> (raw)
In-Reply-To: <20230123104742.227460-5-tomi.valkeinen+renesas@ideasonboard.com>

From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>

According to hardware manual, LVDCR0 register must be cleared bit by bit
when disabling LVDS.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v3:

- Add comment explaining the register clear sequence
---
 drivers/gpu/drm/rcar-du/rcar_lvds.c | 31 +++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
index a11201e4d31b..260ea5d8624e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
@@ -83,6 +83,11 @@ struct rcar_lvds {
 #define bridge_to_rcar_lvds(b) \
 	container_of(b, struct rcar_lvds, bridge)
 
+static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg)
+{
+	return ioread32(lvds->mmio + reg);
+}
+
 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
 {
 	iowrite32(data, lvds->mmio + reg);
@@ -544,6 +549,32 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
 				     struct drm_bridge_state *old_bridge_state)
 {
 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
+	u32 lvdcr0;
+
+	/*
+	 * Clear the LVDCR0 bits in the order specified by the hardware
+	 * documentation, ending with a write of 0 to the full register to
+	 * clear all remaining bits.
+	 */
+	lvdcr0 = rcar_lvds_read(lvds, LVDCR0);
+
+	lvdcr0 &= ~LVDCR0_LVRES;
+	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+
+	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
+		lvdcr0 &= ~LVDCR0_LVEN;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
+
+	if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
+		lvdcr0 &= ~LVDCR0_PWD;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
+
+	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
+		lvdcr0 &= ~LVDCR0_PLLON;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
 
 	rcar_lvds_write(lvds, LVDCR0, 0);
 	rcar_lvds_write(lvds, LVDCR1, 0);
-- 
Regards,

Laurent Pinchart


WARNING: multiple messages have this Message-ID (diff)
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-renesas-soc@vger.kernel.org,
	Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Kieran Bingham <kieran.bingham@ideasonboard.com>,
	Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Subject: [PATCH v3.1 4/7] drm: rcar-du: lvds: Fix stop sequence
Date: Tue, 24 Jan 2023 00:50:13 +0200	[thread overview]
Message-ID: <20230123225013.10476-1-laurent.pinchart+renesas@ideasonboard.com> (raw)
In-Reply-To: <20230123104742.227460-5-tomi.valkeinen+renesas@ideasonboard.com>

From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>

According to hardware manual, LVDCR0 register must be cleared bit by bit
when disabling LVDS.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v3:

- Add comment explaining the register clear sequence
---
 drivers/gpu/drm/rcar-du/rcar_lvds.c | 31 +++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
index a11201e4d31b..260ea5d8624e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
@@ -83,6 +83,11 @@ struct rcar_lvds {
 #define bridge_to_rcar_lvds(b) \
 	container_of(b, struct rcar_lvds, bridge)
 
+static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg)
+{
+	return ioread32(lvds->mmio + reg);
+}
+
 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
 {
 	iowrite32(data, lvds->mmio + reg);
@@ -544,6 +549,32 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
 				     struct drm_bridge_state *old_bridge_state)
 {
 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
+	u32 lvdcr0;
+
+	/*
+	 * Clear the LVDCR0 bits in the order specified by the hardware
+	 * documentation, ending with a write of 0 to the full register to
+	 * clear all remaining bits.
+	 */
+	lvdcr0 = rcar_lvds_read(lvds, LVDCR0);
+
+	lvdcr0 &= ~LVDCR0_LVRES;
+	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+
+	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
+		lvdcr0 &= ~LVDCR0_LVEN;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
+
+	if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
+		lvdcr0 &= ~LVDCR0_PWD;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
+
+	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
+		lvdcr0 &= ~LVDCR0_PLLON;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
 
 	rcar_lvds_write(lvds, LVDCR0, 0);
 	rcar_lvds_write(lvds, LVDCR1, 0);
-- 
Regards,

Laurent Pinchart


  parent reply	other threads:[~2023-01-23 22:50 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-23 10:47 [PATCH v3 0/7] drm: rcar-du: Misc patches Tomi Valkeinen
2023-01-23 10:47 ` Tomi Valkeinen
2023-01-23 10:47 ` [PATCH v3 1/7] drm: rcar-du: dsi: add 'select RESET_CONTROLLER' Tomi Valkeinen
2023-01-23 10:47   ` Tomi Valkeinen
2023-01-23 10:47 ` [PATCH v3 2/7] drm: rcar-du: lvds: Add runtime PM Tomi Valkeinen
2023-01-23 10:47   ` Tomi Valkeinen
2023-01-23 10:47 ` [PATCH v3 3/7] drm: rcar-du: lvds: Add reset control Tomi Valkeinen
2023-01-23 10:47   ` Tomi Valkeinen
2023-01-23 10:47 ` [PATCH v3 4/7] drm: rcar-du: lvds: Fix stop sequence Tomi Valkeinen
2023-01-23 10:47   ` Tomi Valkeinen
2023-01-23 14:28   ` Geert Uytterhoeven
2023-01-23 14:28     ` Geert Uytterhoeven
2023-01-23 22:36     ` Laurent Pinchart
2023-01-23 22:36       ` Laurent Pinchart
2023-01-23 22:50   ` Laurent Pinchart [this message]
2023-01-23 22:50     ` [PATCH v3.1 " Laurent Pinchart
2023-01-23 10:47 ` [PATCH v3 5/7] drm: rcar-du: Add quirk for H3 ES1.x pclk workaround Tomi Valkeinen
2023-01-23 10:47   ` Tomi Valkeinen
2023-01-23 10:47 ` [PATCH v3 6/7] drm: rcar-du: Fix setting a reserved bit in DPLLCR Tomi Valkeinen
2023-01-23 10:47   ` Tomi Valkeinen
2023-01-23 10:47 ` [PATCH v3 7/7] drm: rcar-du: Stop accessing non-existant registers on gen4 Tomi Valkeinen
2023-01-23 10:47   ` Tomi Valkeinen

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