From: Anup Patel <apatel@ventanamicro.com> To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH v2 2/7] RISC-V: Detect AIA CSRs from ISA string Date: Sat, 28 Jan 2023 12:57:32 +0530 [thread overview] Message-ID: <20230128072737.2995881-3-apatel@ventanamicro.com> (raw) In-Reply-To: <20230128072737.2995881-1-apatel@ventanamicro.com> We have two extension names for AIA ISA support: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). We extend the ISA string parsing to detect Smaia and Ssaia extensions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpu.c | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 86328e3acb02..341ef30a3718 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,6 +59,8 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SMAIA, + RISCV_ISA_EXT_SSAIA, RISCV_ISA_EXT_ID_MAX }; static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..a215ec929160 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -162,6 +162,8 @@ arch_initcall(riscv_cpuinfo_init); * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 93e45560af30..3c5b51f519d5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -228,6 +228,8 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); } #undef SET_ISA_EXT_MAP } -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com> To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH v2 2/7] RISC-V: Detect AIA CSRs from ISA string Date: Sat, 28 Jan 2023 12:57:32 +0530 [thread overview] Message-ID: <20230128072737.2995881-3-apatel@ventanamicro.com> (raw) In-Reply-To: <20230128072737.2995881-1-apatel@ventanamicro.com> We have two extension names for AIA ISA support: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). We extend the ISA string parsing to detect Smaia and Ssaia extensions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpu.c | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 86328e3acb02..341ef30a3718 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,6 +59,8 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SMAIA, + RISCV_ISA_EXT_SSAIA, RISCV_ISA_EXT_ID_MAX }; static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..a215ec929160 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -162,6 +162,8 @@ arch_initcall(riscv_cpuinfo_init); * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 93e45560af30..3c5b51f519d5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -228,6 +228,8 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); } #undef SET_ISA_EXT_MAP } -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-28 7:28 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-28 7:27 [PATCH v2 0/7] RISC-V KVM virtualize AIA CSRs Anup Patel 2023-01-28 7:27 ` Anup Patel 2023-01-28 7:27 ` [PATCH v2 1/7] RISC-V: Add AIA related CSR defines Anup Patel 2023-01-28 7:27 ` Anup Patel 2023-01-31 9:22 ` Atish Patra 2023-01-31 9:22 ` Atish Patra 2023-02-03 0:24 ` Palmer Dabbelt 2023-02-03 0:24 ` Palmer Dabbelt 2023-01-28 7:27 ` Anup Patel [this message] 2023-01-28 7:27 ` [PATCH v2 2/7] RISC-V: Detect AIA CSRs from ISA string Anup Patel 2023-01-31 9:25 ` Atish Patra 2023-01-31 9:25 ` Atish Patra 2023-02-03 0:24 ` Palmer Dabbelt 2023-02-03 0:24 ` Palmer Dabbelt 2023-02-03 12:01 ` Anup Patel 2023-02-03 12:01 ` Anup Patel 2023-02-07 18:05 ` Conor Dooley 2023-02-07 18:05 ` Conor Dooley 2023-02-07 18:09 ` Conor Dooley 2023-02-07 18:09 ` Conor Dooley 2023-02-07 18:15 ` Atish Patra 2023-02-07 18:15 ` Atish Patra 2023-02-07 20:39 ` Conor Dooley 2023-02-07 20:39 ` Conor Dooley 2023-02-08 3:54 ` Anup Patel 2023-02-08 3:54 ` Anup Patel 2023-02-08 12:57 ` Conor Dooley 2023-02-08 12:57 ` Conor Dooley 2023-02-08 14:57 ` Anup Patel 2023-02-08 14:57 ` Anup Patel 2023-02-09 23:31 ` Conor Dooley 2023-02-09 23:31 ` Conor Dooley 2023-02-08 3:06 ` Anup Patel 2023-02-08 3:06 ` Anup Patel 2023-02-15 15:41 ` Christoph Müllner 2023-02-15 15:41 ` Christoph Müllner 2023-02-21 7:12 ` Christoph Müllner 2023-02-21 7:12 ` Christoph Müllner 2023-02-21 10:40 ` Conor Dooley 2023-02-21 10:40 ` Conor Dooley 2023-02-21 10:51 ` Jessica Clarke 2023-02-21 10:51 ` Jessica Clarke 2023-02-21 10:59 ` Conor Dooley 2023-02-21 10:59 ` Conor Dooley 2023-02-21 11:03 ` Christoph Müllner 2023-02-21 11:03 ` Christoph Müllner 2023-02-21 11:22 ` Conor Dooley 2023-02-21 11:22 ` Conor Dooley 2023-03-31 12:53 ` Anup Patel 2023-03-31 12:53 ` Anup Patel 2023-01-28 7:27 ` [PATCH v2 3/7] RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID mask defines Anup Patel 2023-01-28 7:27 ` Anup Patel 2023-01-31 9:27 ` Atish Patra 2023-01-31 9:27 ` Atish Patra 2023-01-28 7:27 ` [PATCH v2 4/7] RISC-V: KVM: Initial skeletal support for AIA Anup Patel 2023-01-28 7:27 ` Anup Patel 2023-01-31 9:51 ` Atish Patra 2023-01-31 9:51 ` Atish Patra 2023-01-28 7:27 ` [PATCH v2 5/7] RISC-V: KVM: Add ONE_REG interface for AIA CSRs Anup Patel 2023-01-28 7:27 ` Anup Patel 2023-02-08 0:04 ` Atish Patra 2023-02-08 0:04 ` Atish Patra 2023-03-31 17:15 ` Anup Patel 2023-03-31 17:15 ` Anup Patel 2023-01-28 7:27 ` [PATCH v2 6/7] RISC-V: KVM: Virtualize per-HART " Anup Patel 2023-01-28 7:27 ` Anup Patel 2023-01-28 7:27 ` [PATCH v2 7/7] RISC-V: KVM: Implement guest external interrupt line management Anup Patel 2023-01-28 7:27 ` Anup Patel 2023-02-08 0:15 ` Atish Patra 2023-02-08 0:15 ` Atish Patra 2023-03-31 17:15 ` Anup Patel 2023-03-31 17:15 ` Anup Patel 2023-01-31 6:01 ` [PATCH v2 0/7] RISC-V KVM virtualize AIA CSRs Anup Patel 2023-01-31 6:01 ` Anup Patel
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230128072737.2995881-3-apatel@ventanamicro.com \ --to=apatel@ventanamicro.com \ --cc=ajones@ventanamicro.com \ --cc=anup@brainfault.org \ --cc=atishp@atishpatra.org \ --cc=kvm-riscv@lists.infradead.org \ --cc=kvm@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=pbonzini@redhat.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.