[PATCH v3 0/5] arm64: pseudo-nmi: elide code when CONFIG_ARM64_PSEUDO_NMI=n

From: Mark Rutland <mark.rutland@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: broonie@kernel.org, catalin.marinas@arm.com,
	mark.rutland@arm.com, maz@kernel.org, will@kernel.org
Subject: [PATCH v3 0/5] arm64: pseudo-nmi: elide code when CONFIG_ARM64_PSEUDO_NMI=n
Date: Mon, 30 Jan 2023 14:54:24 +0000	[thread overview]
Message-ID: <20230130145429.903791-1-mark.rutland@arm.com> (raw)

This series addresses a couple of sub-optimal code generation issues with
arm64's pseudo-nmi support code:

* Even when CONFIG_ARM64_PSEUDO_NMI=n, we generate alternative code
  sequences and alt_instr entries which will never be used. This series
  reworks the irqflags code to use alternative branches (with an
  IS_ENABLED() check), which allows the alternatives to be elided when
  CONFIG_ARM64_PSEUDO_NMI=n.

* When PMHE is eanbled in HW, we must synchronize PMR updates using a
  DSB SY. We take pains to avoid this using a static key to skip the
  barrier when PMHE is not in use, but this results in unnecessarily
  branchy code. This series replaces the static key with an alternative,
  allowing the DSB SY to be relaxed to a NOP.

These changes make a defconfig kernel a little smaller, and does not
adversely affect the size of a CONFIG_ARM64_PSEUDO_NMI=y kernel. The
structural changes will also make it easier for a subsequent series to
rework the irqflag and daifflag management, addressing some
long-standing edge cases and preparing for ARMv8.8-A's FEAT_NMI.

I've tested this series under a QEM KVM VM on a ThunderX2 host, and a
QEMU TCG VM on an x86_64 host. I've tested with and without pseudo-NMI
support enabled, and with pseudo-NMI debug and lockdep enabled, using
perf record in system-wide mode.

Since v1 [1]:
* Rename ARM64_HAS_GIC_PRIO_NO_PMHE to ARM64_HAS_GIC_PRIO_RELAXED_SYNC
* Add explanatory comments for cpucap dependencies
* Add patch making ARM64_HAS_GIC_PRIO_MASKING depend on
  ARM64_HAS_GIC_PRIO_MASKING

Since v2 [2]:
* Fix typo in patch 3's subject to refer to ARM64_HAS_GIC_CPUIF_SYSREGS
* Re-home comment regarding PMHE and EL3
* Correct barriers in patch 5
* Explain barrier changes in patch 5's commit message
* Add Reviewed-by tags from Marc

[1] https://lore.kernel.org/linux-arm-kernel/20230123124042.718743-1-mark.rutland@arm.com/
[2] https://lore.kernel.org/linux-arm-kernel/20230125163826.496739-1-mark.rutland@arm.com/

Thanks,
Mark.

Mark Rutland (5):
  arm64: rename ARM64_HAS_SYSREG_GIC_CPUIF to
    ARM64_HAS_GIC_CPUIF_SYSREGS
  arm64: rename ARM64_HAS_IRQ_PRIO_MASKING to ARM64_HAS_GIC_PRIO_MASKING
  arm64: make ARM64_HAS_GIC_PRIO_MASKING depend on
    ARM64_HAS_GIC_CPUIF_SYSREGS
  arm64: add ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucap
  arm64: irqflags: use alternative branches for pseudo-NMI logic

 arch/arm/include/asm/arch_gicv3.h   |   5 +
 arch/arm64/include/asm/arch_gicv3.h |   5 +
 arch/arm64/include/asm/barrier.h    |  11 +-
 arch/arm64/include/asm/cpufeature.h |   2 +-
 arch/arm64/include/asm/irqflags.h   | 191 +++++++++++++++++++---------
 arch/arm64/include/asm/ptrace.h     |   2 +-
 arch/arm64/kernel/cpufeature.c      |  55 ++++++--
 arch/arm64/kernel/entry.S           |  25 ++--
 arch/arm64/kernel/image-vars.h      |   2 -
 arch/arm64/tools/cpucaps            |   5 +-
 drivers/irqchip/irq-gic-v3.c        |  19 +--
 drivers/irqchip/irq-gic.c           |   2 +-
 12 files changed, 219 insertions(+), 105 deletions(-)

-- 
2.30.2

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