From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, cota@braap.org
Subject: [PATCH 19/27] target/hexagon: Don't use tcg_temp_local_new_*
Date: Mon, 30 Jan 2023 10:59:27 -1000 [thread overview]
Message-ID: <20230130205935.1157347-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230130205935.1157347-1-richard.henderson@linaro.org>
Since tcg_temp_new_* is now identical, use those.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/idef-parser/README.rst | 4 ++--
target/hexagon/gen_tcg.h | 4 ++--
target/hexagon/genptr.c | 16 ++++++++--------
target/hexagon/idef-parser/parser-helpers.c | 4 ++--
target/hexagon/translate.c | 2 +-
target/hexagon/README | 8 ++++----
target/hexagon/gen_tcg_funcs.py | 18 +++++++-----------
7 files changed, 26 insertions(+), 30 deletions(-)
diff --git a/target/hexagon/idef-parser/README.rst b/target/hexagon/idef-parser/README.rst
index ff6d14150a..c230fec124 100644
--- a/target/hexagon/idef-parser/README.rst
+++ b/target/hexagon/idef-parser/README.rst
@@ -294,9 +294,9 @@ generators the previous declarations are mapped to
::
- int var1; -> TCGv_i32 var1 = tcg_temp_local_new_i32();
+ int var1; -> TCGv_i32 var1 = tcg_temp_new_i32();
- int var2 = 0; -> TCGv_i32 var1 = tcg_temp_local_new_i32();
+ int var2 = 0; -> TCGv_i32 var1 = tcg_temp_new_i32();
tcg_gen_movi_i32(j, ((int64_t) 0ULL));
which are later automatically freed at the end of the function they're declared
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 19697b42a5..a219a7f5dd 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -337,7 +337,7 @@
*/
#define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \
do { \
- TCGv LSB = tcg_temp_local_new(); \
+ TCGv LSB = tcg_temp_new(); \
TCGLabel *label = gen_new_label(); \
tcg_gen_movi_tl(EA, 0); \
PRED; \
@@ -397,7 +397,7 @@
/* Predicated loads into a register pair */
#define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \
do { \
- TCGv LSB = tcg_temp_local_new(); \
+ TCGv LSB = tcg_temp_new(); \
TCGLabel *label = gen_new_label(); \
tcg_gen_movi_tl(EA, 0); \
PRED; \
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 90db99024f..591461b043 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -706,7 +706,7 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred,
TCGCond cond, int pc_off)
{
TCGv next_PC;
- TCGv lsb = tcg_temp_local_new();
+ TCGv lsb = tcg_temp_new();
TCGLabel *skip = gen_new_label();
tcg_gen_andi_tl(lsb, pred, 1);
gen_write_new_pc_pcrel(ctx, pc_off, cond, lsb);
@@ -720,7 +720,7 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred,
static void gen_endloop0(DisasContext *ctx)
{
- TCGv lpcfg = tcg_temp_local_new();
+ TCGv lpcfg = tcg_temp_new();
GET_USR_FIELD(USR_LPCFG, lpcfg);
@@ -852,7 +852,7 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
/* Bidirectional shift right with saturation */
static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
{
- TCGv shift_amt = tcg_temp_local_new();
+ TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
TCGLabel *done = gen_new_label();
@@ -876,7 +876,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
/* Bidirectional shift left with saturation */
static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
{
- TCGv shift_amt = tcg_temp_local_new();
+ TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
TCGLabel *done = gen_new_label();
@@ -918,7 +918,7 @@ static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num,
intptr_t dstoff;
if (is_predicated) {
- TCGv cancelled = tcg_temp_local_new();
+ TCGv cancelled = tcg_temp_new();
label_end = gen_new_label();
/* Don't do anything if the slot was cancelled */
@@ -959,7 +959,7 @@ static void gen_log_qreg_write(intptr_t srcoff, int num, int vnew,
intptr_t dstoff;
if (is_predicated) {
- TCGv cancelled = tcg_temp_local_new();
+ TCGv cancelled = tcg_temp_new();
label_end = gen_new_label();
/* Don't do anything if the slot was cancelled */
@@ -1164,10 +1164,10 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
/* Implements the fADDSAT64 macro in TCG */
void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
- TCGv_i64 sum = tcg_temp_local_new_i64();
+ TCGv_i64 sum = tcg_temp_new_i64();
TCGv_i64 xor = tcg_temp_new_i64();
TCGv_i64 cond1 = tcg_temp_new_i64();
- TCGv_i64 cond2 = tcg_temp_local_new_i64();
+ TCGv_i64 cond2 = tcg_temp_new_i64();
TCGv_i64 cond3 = tcg_temp_new_i64();
TCGv_i64 mask = tcg_constant_i64(0x8000000000000000ULL);
TCGv_i64 max_pos = tcg_constant_i64(0x7FFFFFFFFFFFFFFFLL);
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
index 8110686c51..dfb9c65b52 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -322,7 +322,7 @@ HexValue gen_tmp_local(Context *c,
rvalue.is_manual = false;
rvalue.tmp.index = c->inst.tmp_count;
OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count,
- " = tcg_temp_local_new_i", &bit_width, "();\n");
+ " = tcg_temp_new_i", &bit_width, "();\n");
c->inst.tmp_count++;
return rvalue;
}
@@ -554,7 +554,7 @@ void gen_varid_allocate(Context *c,
new_var.signedness = signedness;
EMIT_HEAD(c, "TCGv_%s %s", bit_suffix, varid->var.name->str);
- EMIT_HEAD(c, " = tcg_temp_local_new_%s();\n", bit_suffix);
+ EMIT_HEAD(c, " = tcg_temp_new_%s();\n", bit_suffix);
g_array_append_val(c->inst.allocated, new_var);
}
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index fc3061a540..381fdaa3a8 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -539,7 +539,7 @@ void process_store(DisasContext *ctx, int slot_num)
tcg_temp_free(cancelled);
}
{
- TCGv address = tcg_temp_local_new();
+ TCGv address = tcg_temp_new();
tcg_gen_mov_tl(address, hex_store_addr[slot_num]);
/*
diff --git a/target/hexagon/README b/target/hexagon/README
index 6cb5affddb..2e32639fb7 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -81,7 +81,7 @@ tcg_funcs_generated.c.inc
Insn *insn,
Packet *pkt)
{
- TCGv RdV = tcg_temp_local_new();
+ TCGv RdV = tcg_temp_new();
const int RdN = insn->regno[0];
TCGv RsV = hex_gpr[insn->regno[1]];
TCGv RtV = hex_gpr[insn->regno[2]];
@@ -146,16 +146,16 @@ istruction.
const int VdN = insn->regno[0];
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, VdN, 1, true);
- TCGv_ptr VdV = tcg_temp_local_new_ptr();
+ TCGv_ptr VdV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VdV, cpu_env, VdV_off);
const int VuN = insn->regno[1];
const intptr_t VuV_off =
vreg_src_off(ctx, VuN);
- TCGv_ptr VuV = tcg_temp_local_new_ptr();
+ TCGv_ptr VuV = tcg_temp_new_ptr();
const int VvN = insn->regno[2];
const intptr_t VvV_off =
vreg_src_off(ctx, VvN);
- TCGv_ptr VvV = tcg_temp_local_new_ptr();
+ TCGv_ptr VvV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VuV, cpu_env, VuV_off);
tcg_gen_addi_ptr(VvV, cpu_env, VvV_off);
TCGv slot = tcg_constant_tl(insn->slot);
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index 7e8ba17ca2..dfc90712fb 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -26,18 +26,14 @@
## Helpers for gen_tcg_func
##
def gen_decl_ea_tcg(f, tag):
- if ('A_CONDEXEC' in hex_common.attribdict[tag] or
- 'A_LOAD' in hex_common.attribdict[tag]):
- f.write(" TCGv EA = tcg_temp_local_new();\n")
- else:
- f.write(" TCGv EA = tcg_temp_new();\n")
+ f.write(" TCGv EA = tcg_temp_new();\n")
def gen_free_ea_tcg(f):
f.write(" tcg_temp_free(EA);\n")
def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
- f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
+ f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
if (regtype == "C"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
@@ -56,7 +52,7 @@ def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
def genptr_decl_writable(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
- f.write(" TCGv %s%sV = tcg_temp_local_new();\n" % \
+ f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
(regtype, regid))
if (regtype == "C"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
@@ -73,7 +69,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
if (regtype == "R"):
if (regid in {"ss", "tt"}):
- f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
+ f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
@@ -96,14 +92,14 @@ def genptr_decl(f, tag, regtype, regid, regno):
print("Bad register parse: ", regtype, regid)
elif (regtype == "C"):
if (regid == "ss"):
- f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
+ f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
elif (regid == "dd"):
genptr_decl_pair_writable(f, tag, regtype, regid, regno)
elif (regid == "s"):
- f.write(" TCGv %s%sV = tcg_temp_local_new();\n" % \
+ f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
(regtype, regid))
f.write(" const int %s%sN = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regtype, regid, regno))
@@ -575,7 +571,7 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
## We produce:
## static void generate_A2_add(DisasContext *ctx)
## {
-## TCGv RdV = tcg_temp_local_new();
+## TCGv RdV = tcg_temp_new();
## const int RdN = insn->regno[0];
## TCGv RsV = hex_gpr[insn->regno[1]];
## TCGv RtV = hex_gpr[insn->regno[2]];
--
2.34.1
next prev parent reply other threads:[~2023-01-30 21:04 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-30 20:59 [PATCH 00/27] tcg: Simplify temporary usage Richard Henderson
2023-01-30 20:59 ` [PATCH] target/arm: Fix physical address resolution for Stage2 Richard Henderson
2023-01-30 21:00 ` Richard Henderson
2023-01-30 20:59 ` [PATCH 01/27] tcg: Adjust TCGContext.temps_in_use check Richard Henderson
2023-01-30 23:30 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 02/27] accel/tcg: Pass max_insn to gen_intermediate_code by pointer Richard Henderson
2023-02-16 7:24 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 03/27] accel/tcg: Use more accurate max_insns for tb_overflow Richard Henderson
2023-01-30 20:59 ` [PATCH 04/27] tcg: Remove branch-to-next regardless of reference count Richard Henderson
2023-01-30 20:59 ` [PATCH 05/27] tcg: Rename TEMP_LOCAL to TEMP_TB Richard Henderson
2023-01-30 23:34 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 06/27] tcg: Add liveness_pass_0 Richard Henderson
2023-01-30 20:59 ` [PATCH 07/27] tcg: Remove TEMP_NORMAL Richard Henderson
2023-01-30 23:36 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 08/27] tcg: Pass TCGTempKind to tcg_temp_new_internal Richard Henderson
2023-01-30 23:36 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 09/27] tcg: Add tcg_temp_ebb_new_{i32,i64,ptr} Richard Henderson
2023-01-30 23:59 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 10/27] tcg: Add tcg_gen_movi_ptr Richard Henderson
2023-02-16 7:15 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 11/27] tcg: Use tcg_temp_ebb_new_* in tcg/ Richard Henderson
2023-01-30 23:59 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 12/27] accel/tcg/plugin: Use tcg_temp_ebb_* Richard Henderson
2023-02-16 7:22 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 13/27] accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers Richard Henderson
2023-01-30 23:39 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 14/27] tcg: Don't re-use TEMP_TB temporaries Richard Henderson
2023-01-30 20:59 ` [PATCH 15/27] tcg: Change default temp lifetime to TEMP_TB Richard Henderson
2023-01-30 23:52 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 16/27] target/arm: Drop copies in gen_sve_{ldr,str} Richard Henderson
2023-01-30 20:59 ` [PATCH 17/27] target/arm: Don't use tcg_temp_local_new_* Richard Henderson
2023-01-30 23:44 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 18/27] target/cris: Don't use tcg_temp_local_new Richard Henderson
2023-01-30 23:43 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` Richard Henderson [this message]
2023-01-30 23:43 ` [PATCH 19/27] target/hexagon: Don't use tcg_temp_local_new_* Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 20/27] target/hppa: Don't use tcg_temp_local_new Richard Henderson
2023-01-30 23:41 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 21/27] target/i386: " Richard Henderson
2023-02-16 7:13 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 22/27] target/mips: " Richard Henderson
2023-01-30 23:42 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 23/27] target/ppc: " Richard Henderson
2023-01-30 23:43 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 24/27] target/xtensa: Don't use tcg_temp_local_new_* Richard Henderson
2023-01-30 23:44 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 25/27] exec/gen-icount: Don't use tcg_temp_local_new_i32 Richard Henderson
2023-01-30 23:45 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 26/27] tcg: Remove tcg_temp_local_new_*, tcg_const_local_* Richard Henderson
2023-01-30 23:45 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 27/27] tcg: Update docs/devel/tcg-ops.rst for temporary changes Richard Henderson
2023-02-10 12:35 ` [PATCH 00/27] tcg: Simplify temporary usage Emilio Cota
2023-02-16 6:15 ` Richard Henderson
2023-03-01 12:11 ` Emilio Cota
2023-02-16 6:11 ` Richard Henderson
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