From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, cota@braap.org
Subject: [PATCH 02/27] accel/tcg: Pass max_insn to gen_intermediate_code by pointer
Date: Mon, 30 Jan 2023 10:59:10 -1000 [thread overview]
Message-ID: <20230130205935.1157347-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230130205935.1157347-1-richard.henderson@linaro.org>
In preparation for returning the number of insns generated
via the same pointer. Adjust only the prototypes so far.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/translator.h | 4 ++--
accel/tcg/translate-all.c | 2 +-
accel/tcg/translator.c | 4 ++--
target/alpha/translate.c | 2 +-
target/arm/translate.c | 2 +-
target/avr/translate.c | 2 +-
target/cris/translate.c | 2 +-
target/hexagon/translate.c | 2 +-
target/hppa/translate.c | 2 +-
target/i386/tcg/translate.c | 2 +-
target/loongarch/translate.c | 2 +-
target/m68k/translate.c | 2 +-
target/microblaze/translate.c | 2 +-
target/mips/tcg/translate.c | 2 +-
target/nios2/translate.c | 2 +-
target/openrisc/translate.c | 2 +-
target/ppc/translate.c | 2 +-
target/riscv/translate.c | 2 +-
target/rx/translate.c | 2 +-
target/s390x/tcg/translate.c | 2 +-
target/sh4/translate.c | 2 +-
target/sparc/translate.c | 2 +-
target/tricore/translate.c | 2 +-
target/xtensa/translate.c | 2 +-
24 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index af2ff95cd5..8b36690e80 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -37,7 +37,7 @@
* This function must be provided by the target, which should create
* the target-specific DisasContext, and then invoke translator_loop.
*/
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc);
/**
@@ -146,7 +146,7 @@ typedef struct TranslatorOps {
* - When single-stepping is enabled (system-wide or on the current vCPU).
* - When too many instructions have been translated.
*/
-void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc,
const TranslatorOps *ops, DisasContextBase *db);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 9e925c10f3..b7b361959e 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -281,7 +281,7 @@ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb,
tcg_func_start(tcg_ctx);
tcg_ctx->cpu = env_cpu(env);
- gen_intermediate_code(env_cpu(env), tb, *max_insns, pc, host_pc);
+ gen_intermediate_code(env_cpu(env), tb, max_insns, pc, host_pc);
assert(tb->size != 0);
tcg_ctx->cpu = NULL;
*max_insns = tb->icount;
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 061519691f..08a816bffe 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -42,7 +42,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
}
-void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc,
const TranslatorOps *ops, DisasContextBase *db)
{
@@ -55,7 +55,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
db->pc_next = pc;
db->is_jmp = DISAS_NEXT;
db->num_insns = 0;
- db->max_insns = max_insns;
+ db->max_insns = *max_insns;
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
db->host_addr[0] = host_pc;
db->host_addr[1] = NULL;
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index f9bcdeb717..716b083f39 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -3043,7 +3043,7 @@ static const TranslatorOps alpha_tr_ops = {
.disas_log = alpha_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 365e02fb0b..12eeada122 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9937,7 +9937,7 @@ static const TranslatorOps thumb_translator_ops = {
};
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc = { };
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 2bed56f135..e40d8e9681 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -3049,7 +3049,7 @@ static const TranslatorOps avr_tr_ops = {
.disas_log = avr_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc = { };
diff --git a/target/cris/translate.c b/target/cris/translate.c
index fbc3fd5865..905d01288e 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3286,7 +3286,7 @@ static const TranslatorOps cris_tr_ops = {
.disas_log = cris_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 75f28e08ad..fc3061a540 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -962,7 +962,7 @@ static const TranslatorOps hexagon_tr_ops = {
.disas_log = hexagon_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 981f8ee03d..0102cf451b 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4359,7 +4359,7 @@ static const TranslatorOps hppa_tr_ops = {
.disas_log = hppa_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9d9392b009..a47d60f057 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -7158,7 +7158,7 @@ static const TranslatorOps i386_tr_ops = {
};
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 38ced69803..bc7cff5f3f 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -246,7 +246,7 @@ static const TranslatorOps loongarch_tr_ops = {
.disas_log = loongarch_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 18418312b1..9e6b6d07d0 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6389,7 +6389,7 @@ static const TranslatorOps m68k_tr_ops = {
.disas_log = m68k_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 974f21eb31..037a652cb9 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1849,7 +1849,7 @@ static const TranslatorOps mb_tr_ops = {
.disas_log = mb_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 624e6b7786..6dbd262ebc 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16160,7 +16160,7 @@ static const TranslatorOps mips_tr_ops = {
.disas_log = mips_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 4db8b47744..b0dab8d460 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -1039,7 +1039,7 @@ static const TranslatorOps nios2_tr_ops = {
.disas_log = nios2_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 2f3d7c5fd1..b8cd8e0964 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1705,7 +1705,7 @@ static const TranslatorOps openrisc_tr_ops = {
.disas_log = openrisc_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1c17d5a558..5fe6aa641e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7707,7 +7707,7 @@ static const TranslatorOps ppc_tr_ops = {
.disas_log = ppc_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 01cc30a365..479fc2b128 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1277,7 +1277,7 @@ static const TranslatorOps riscv_tr_ops = {
.disas_log = riscv_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 87a3f54adb..af23876cb3 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2363,7 +2363,7 @@ static const TranslatorOps rx_tr_ops = {
.disas_log = rx_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index ac5bd98f04..339c1672e9 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -6759,7 +6759,7 @@ static const TranslatorOps s390x_tr_ops = {
.disas_log = s390x_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 7db3468b01..23563024e0 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2374,7 +2374,7 @@ static const TranslatorOps sh4_tr_ops = {
.disas_log = sh4_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 150aeecd14..3b0044aa66 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5904,7 +5904,7 @@ static const TranslatorOps sparc_tr_ops = {
.disas_log = sparc_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc = {};
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index df9e46c649..59d48faf11 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8878,7 +8878,7 @@ static const TranslatorOps tricore_tr_ops = {
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 77bcd71030..8d7bf566de 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1279,7 +1279,7 @@ static const TranslatorOps xtensa_translator_ops = {
.disas_log = xtensa_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc = {};
--
2.34.1
next prev parent reply other threads:[~2023-01-30 21:02 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-30 20:59 [PATCH 00/27] tcg: Simplify temporary usage Richard Henderson
2023-01-30 20:59 ` [PATCH] target/arm: Fix physical address resolution for Stage2 Richard Henderson
2023-01-30 21:00 ` Richard Henderson
2023-01-30 20:59 ` [PATCH 01/27] tcg: Adjust TCGContext.temps_in_use check Richard Henderson
2023-01-30 23:30 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` Richard Henderson [this message]
2023-02-16 7:24 ` [PATCH 02/27] accel/tcg: Pass max_insn to gen_intermediate_code by pointer Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 03/27] accel/tcg: Use more accurate max_insns for tb_overflow Richard Henderson
2023-01-30 20:59 ` [PATCH 04/27] tcg: Remove branch-to-next regardless of reference count Richard Henderson
2023-01-30 20:59 ` [PATCH 05/27] tcg: Rename TEMP_LOCAL to TEMP_TB Richard Henderson
2023-01-30 23:34 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 06/27] tcg: Add liveness_pass_0 Richard Henderson
2023-01-30 20:59 ` [PATCH 07/27] tcg: Remove TEMP_NORMAL Richard Henderson
2023-01-30 23:36 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 08/27] tcg: Pass TCGTempKind to tcg_temp_new_internal Richard Henderson
2023-01-30 23:36 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 09/27] tcg: Add tcg_temp_ebb_new_{i32,i64,ptr} Richard Henderson
2023-01-30 23:59 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 10/27] tcg: Add tcg_gen_movi_ptr Richard Henderson
2023-02-16 7:15 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 11/27] tcg: Use tcg_temp_ebb_new_* in tcg/ Richard Henderson
2023-01-30 23:59 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 12/27] accel/tcg/plugin: Use tcg_temp_ebb_* Richard Henderson
2023-02-16 7:22 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 13/27] accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers Richard Henderson
2023-01-30 23:39 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 14/27] tcg: Don't re-use TEMP_TB temporaries Richard Henderson
2023-01-30 20:59 ` [PATCH 15/27] tcg: Change default temp lifetime to TEMP_TB Richard Henderson
2023-01-30 23:52 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 16/27] target/arm: Drop copies in gen_sve_{ldr,str} Richard Henderson
2023-01-30 20:59 ` [PATCH 17/27] target/arm: Don't use tcg_temp_local_new_* Richard Henderson
2023-01-30 23:44 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 18/27] target/cris: Don't use tcg_temp_local_new Richard Henderson
2023-01-30 23:43 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 19/27] target/hexagon: Don't use tcg_temp_local_new_* Richard Henderson
2023-01-30 23:43 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 20/27] target/hppa: Don't use tcg_temp_local_new Richard Henderson
2023-01-30 23:41 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 21/27] target/i386: " Richard Henderson
2023-02-16 7:13 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 22/27] target/mips: " Richard Henderson
2023-01-30 23:42 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 23/27] target/ppc: " Richard Henderson
2023-01-30 23:43 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 24/27] target/xtensa: Don't use tcg_temp_local_new_* Richard Henderson
2023-01-30 23:44 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 25/27] exec/gen-icount: Don't use tcg_temp_local_new_i32 Richard Henderson
2023-01-30 23:45 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 26/27] tcg: Remove tcg_temp_local_new_*, tcg_const_local_* Richard Henderson
2023-01-30 23:45 ` Philippe Mathieu-Daudé
2023-01-30 20:59 ` [PATCH 27/27] tcg: Update docs/devel/tcg-ops.rst for temporary changes Richard Henderson
2023-02-10 12:35 ` [PATCH 00/27] tcg: Simplify temporary usage Emilio Cota
2023-02-16 6:15 ` Richard Henderson
2023-03-01 12:11 ` Emilio Cota
2023-02-16 6:11 ` Richard Henderson
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