From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, pbonzini@redhat.com,
philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Subject: [PATCH 00/39] Add RISC-V vector cryptography extensions
Date: Thu, 2 Feb 2023 12:41:51 +0000 [thread overview]
Message-ID: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> (raw)
This patch series introduces an implementation for the six instruction sets
of the draft RISC-V vector cryptography extensions specification.
This patch set implements the instruction sets as per the 20221202
version of the specification (1). We plan to update to the latest spec
once stabilised.
Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Codethink
sponsored by SiFive, as well as Max Chou and Frank Chang from SiFive.
For convenience we have created a git repo with our patches on top of a
recent master. https://github.com/CodethinkLabs/qemu-ct
1. https://github.com/riscv/riscv-crypto/releases
Dickon Hood (1):
target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding,
translation and execution support
Kiran Ostrolenk (4):
target/riscv: Add vsha2ms.vv decoding, translation and execution
support
target/riscv: add zvksh cpu property
target/riscv: Add vsm3c.vi decoding, translation and execution support
target/riscv: expose zvksh cpu property
Lawrence Hunter (16):
target/riscv: Add vclmul.vv decoding, translation and execution
support
target/riscv: Add vclmul.vx decoding, translation and execution
support
target/riscv: Add vclmulh.vv decoding, translation and execution
support
target/riscv: Add vclmulh.vx decoding, translation and execution
support
target/riscv: Add vaesef.vv decoding, translation and execution
support
target/riscv: Add vaesef.vs decoding, translation and execution
support
target/riscv: Add vaesdf.vv decoding, translation and execution
support
target/riscv: Add vaesdf.vs decoding, translation and execution
support
target/riscv: Add vaesdm.vv decoding, translation and execution
support
target/riscv: Add vaesdm.vs decoding, translation and execution
support
target/riscv: Add vaesz.vs decoding, translation and execution support
target/riscv: Add vsha2c[hl].vv decoding, translation and execution
support
target/riscv: Add vsm3me.vv decoding, translation and execution
support
target/riscv: add zvkg cpu property
target/riscv: Add vghmac.vv decoding, translation and execution
support
target/riscv: expose zvkg cpu property
Max Chou (5):
crypto: Move SM4_SBOXWORD from target/riscv
crypto: Add SM4 constant parameter CK.
target/riscv: Add zvksed cfg property
target/riscv: Add Zvksed support
target/riscv: Expose Zvksed property
Nazar Kazakov (10):
target/riscv: add zvkb cpu property
target/riscv: Add vrev8.v decoding, translation and execution support
target/riscv: Add vandn.[vv,vx,vi] decoding, translation and execution
support
target/riscv: expose zvkb cpu property
target/riscv: add zvkns cpu property
target/riscv: Add vaeskf1.vi decoding, translation and execution
support
target/riscv: Add vaeskf2.vi decoding, translation and execution
support
target/riscv: expose zvkns cpu property
target/riscv: add zvknh cpu properties
target/riscv: expose zvknh cpu properties
William Salmon (3):
target/riscv: Add vbrev8.v decoding, translation and execution support
target/riscv: Add vaesem.vv decoding, translation and execution
support
target/riscv: Add vaesem.vs decoding, translation and execution
support
crypto/sm4.c | 10 +
include/crypto/sm4.h | 8 +
include/qemu/bitops.h | 32 +
target/arm/crypto_helper.c | 10 +-
target/riscv/cpu.c | 33 +
target/riscv/cpu.h | 7 +
target/riscv/crypto_helper.c | 1 +
target/riscv/helper.h | 69 ++
target/riscv/insn32.decode | 48 +
target/riscv/insn_trans/trans_rvzvkb.c.inc | 162 +++
target/riscv/insn_trans/trans_rvzvkg.c.inc | 9 +
target/riscv/insn_trans/trans_rvzvknh.c.inc | 47 +
target/riscv/insn_trans/trans_rvzvkns.c.inc | 119 ++
target/riscv/insn_trans/trans_rvzvksed.c.inc | 35 +
target/riscv/insn_trans/trans_rvzvksh.c.inc | 20 +
target/riscv/meson.build | 4 +-
target/riscv/translate.c | 6 +
target/riscv/vcrypto_helper.c | 1013 ++++++++++++++++++
target/riscv/vector_helper.c | 242 +----
target/riscv/vector_internals.c | 63 ++
target/riscv/vector_internals.h | 226 ++++
21 files changed, 1914 insertions(+), 250 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc
create mode 100644 target/riscv/vcrypto_helper.c
create mode 100644 target/riscv/vector_internals.c
create mode 100644 target/riscv/vector_internals.h
--
2.39.1
next reply other threads:[~2023-02-02 12:45 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-02 12:41 Lawrence Hunter [this message]
2023-02-02 12:41 ` [PATCH 01/39] target/riscv: add zvkb cpu property Lawrence Hunter
2023-02-02 12:41 ` [PATCH 02/39] target/riscv: Add vclmul.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 13:53 ` Philipp Tomsich
2023-02-02 12:41 ` [PATCH 03/39] target/riscv: Add vclmul.vx " Lawrence Hunter
2023-02-02 13:59 ` Philipp Tomsich
2023-02-02 12:41 ` [PATCH 04/39] target/riscv: Add vclmulh.vv " Lawrence Hunter
2023-02-02 14:03 ` Philipp Tomsich
2023-02-02 16:54 ` Richard Henderson
2023-02-02 12:41 ` [PATCH 05/39] target/riscv: Add vclmulh.vx " Lawrence Hunter
2023-02-02 12:41 ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Lawrence Hunter
2023-02-02 12:41 ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Lawrence Hunter
2023-02-02 14:13 ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Philipp Tomsich
2023-02-02 14:13 ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Philipp Tomsich
2023-02-02 14:30 ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Philipp Tomsich
2023-02-02 14:30 ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Philipp Tomsich
2023-02-02 17:35 ` Richard Henderson
2023-02-02 18:07 ` Philipp Tomsich
2023-02-02 23:14 ` Richard Henderson
2023-02-02 12:41 ` [PATCH 07/39] target/riscv: Add vbrev8.v " Lawrence Hunter
2023-02-02 14:21 ` Philipp Tomsich
2023-02-02 12:41 ` [PATCH 08/39] target/riscv: Add vrev8.v " Lawrence Hunter
2023-02-02 14:22 ` Philipp Tomsich
2023-02-02 12:42 ` [PATCH 09/39] target/riscv: Add vandn.[vv,vx,vi] " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 09/39] target/riscv: Add vandn.[vv, vx, vi] " Lawrence Hunter
2023-02-02 14:29 ` [PATCH 09/39] target/riscv: Add vandn.[vv,vx,vi] " Philipp Tomsich
2023-02-02 12:42 ` [PATCH 10/39] target/riscv: expose zvkb cpu property Lawrence Hunter
2023-02-02 14:23 ` Philipp Tomsich
2023-02-02 14:24 ` Philipp Tomsich
2023-02-02 12:42 ` [PATCH 11/39] target/riscv: add zvkns " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 12/39] target/riscv: Add vaesef.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 13/39] target/riscv: Add vaesef.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 14/39] target/riscv: Add vaesdf.vv " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 15/39] target/riscv: Add vaesdf.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 16/39] target/riscv: Add vaesdm.vv " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 17/39] target/riscv: Add vaesdm.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 18/39] target/riscv: Add vaesz.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 19/39] target/riscv: Add vaesem.vv " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 20/39] target/riscv: Add vaesem.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 21/39] target/riscv: Add vaeskf1.vi " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 22/39] target/riscv: Add vaeskf2.vi " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 23/39] target/riscv: expose zvkns cpu property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 24/39] target/riscv: add zvknh cpu properties Lawrence Hunter
2023-02-02 12:42 ` [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 26/39] target/riscv: Add vsha2c[hl].vv " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 27/39] target/riscv: expose zvknh cpu properties Lawrence Hunter
2023-02-02 12:42 ` [PATCH 28/39] target/riscv: add zvksh cpu property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 30/39] target/riscv: Add vsm3c.vi " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 31/39] target/riscv: expose zvksh cpu property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 32/39] target/riscv: add zvkg " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 34/39] target/riscv: expose zvkg cpu property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 35/39] crypto: Move SM4_SBOXWORD from target/riscv Lawrence Hunter
2023-02-02 17:02 ` Richard Henderson
2023-02-02 12:42 ` [PATCH 36/39] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-02-02 12:42 ` [PATCH 37/39] target/riscv: Add zvksed cfg property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 38/39] target/riscv: Add Zvksed support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 39/39] target/riscv: Expose Zvksed property Lawrence Hunter
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