From: Lawrence Hunter <lawrence.hunter@codethink.co.uk> To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 09/39] target/riscv: Add vandn.[vv,vx,vi] decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:00 +0000 [thread overview] Message-ID: <20230202124230.295997-10-lawrence.hunter@codethink.co.uk> (raw) In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> --- target/riscv/helper.h | 9 +++++++++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvzvkb.c.inc | 5 +++++ target/riscv/vcrypto_helper.c | 19 +++++++++++++++++++ 4 files changed, 36 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c980d52828..5de615ea78 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1171,3 +1171,12 @@ DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 342199abc0..d6f5e4d198 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -904,3 +904,6 @@ vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm +vandn_vi 000001 . ..... ..... 011 ..... 1010111 @r_vm +vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm +vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index 18b362db92..a973b27bdd 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -147,6 +147,11 @@ static bool trans_##NAME(DisasContext *s, arg_rmr * a) \ return false; \ } + +GEN_OPIVV_TRANS(vandn_vv, zvkb_vv_check) +GEN_OPIVX_TRANS(vandn_vx, zvkb_vx_check) +GEN_OPIVI_TRANS(vandn_vi, IMM_SX, vandn_vx, zvkb_vx_check) + static bool vxrev8_check(DisasContext *s, arg_rmr *a) { return s->cfg_ptr->ext_zvkb == true && vext_check_isa_ill(s) && diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index b09fe5fa2a..900e68dfb0 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -135,3 +135,22 @@ GEN_VEXT_V(vrev8_v_b, 1) GEN_VEXT_V(vrev8_v_h, 2) GEN_VEXT_V(vrev8_v_w, 4) GEN_VEXT_V(vrev8_v_d, 8) + +#define DO_ANDN(a, b) ((b) & ~(a)) +RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN) +GEN_VEXT_VV(vandn_vv_b, 1) +GEN_VEXT_VV(vandn_vv_h, 2) +GEN_VEXT_VV(vandn_vv_w, 4) +GEN_VEXT_VV(vandn_vv_d, 8) + +RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN) +GEN_VEXT_VX(vandn_vx_b, 1) +GEN_VEXT_VX(vandn_vx_h, 2) +GEN_VEXT_VX(vandn_vx_w, 4) +GEN_VEXT_VX(vandn_vx_d, 8) -- 2.39.1
WARNING: multiple messages have this Message-ID (diff)
From: Lawrence Hunter <lawrence.hunter@codethink.co.uk> To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 09/39] target/riscv: Add vandn.[vv, vx, vi] decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:00 +0000 [thread overview] Message-ID: <20230202124230.295997-10-lawrence.hunter@codethink.co.uk> (raw) In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> --- target/riscv/helper.h | 9 +++++++++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvzvkb.c.inc | 5 +++++ target/riscv/vcrypto_helper.c | 19 +++++++++++++++++++ 4 files changed, 36 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c980d52828..5de615ea78 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1171,3 +1171,12 @@ DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 342199abc0..d6f5e4d198 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -904,3 +904,6 @@ vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm +vandn_vi 000001 . ..... ..... 011 ..... 1010111 @r_vm +vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm +vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index 18b362db92..a973b27bdd 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -147,6 +147,11 @@ static bool trans_##NAME(DisasContext *s, arg_rmr * a) \ return false; \ } + +GEN_OPIVV_TRANS(vandn_vv, zvkb_vv_check) +GEN_OPIVX_TRANS(vandn_vx, zvkb_vx_check) +GEN_OPIVI_TRANS(vandn_vi, IMM_SX, vandn_vx, zvkb_vx_check) + static bool vxrev8_check(DisasContext *s, arg_rmr *a) { return s->cfg_ptr->ext_zvkb == true && vext_check_isa_ill(s) && diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index b09fe5fa2a..900e68dfb0 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -135,3 +135,22 @@ GEN_VEXT_V(vrev8_v_b, 1) GEN_VEXT_V(vrev8_v_h, 2) GEN_VEXT_V(vrev8_v_w, 4) GEN_VEXT_V(vrev8_v_d, 8) + +#define DO_ANDN(a, b) ((b) & ~(a)) +RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN) +GEN_VEXT_VV(vandn_vv_b, 1) +GEN_VEXT_VV(vandn_vv_h, 2) +GEN_VEXT_VV(vandn_vv_w, 4) +GEN_VEXT_VV(vandn_vv_d, 8) + +RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN) +GEN_VEXT_VX(vandn_vx_b, 1) +GEN_VEXT_VX(vandn_vx_h, 2) +GEN_VEXT_VX(vandn_vx_w, 4) +GEN_VEXT_VX(vandn_vx_d, 8) -- 2.39.1
next prev parent reply other threads:[~2023-02-02 12:45 UTC|newest] Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-02 12:41 [PATCH 00/39] Add RISC-V vector cryptography extensions Lawrence Hunter 2023-02-02 12:41 ` [PATCH 01/39] target/riscv: add zvkb cpu property Lawrence Hunter 2023-02-02 12:41 ` [PATCH 02/39] target/riscv: Add vclmul.vv decoding, translation and execution support Lawrence Hunter 2023-02-02 13:53 ` Philipp Tomsich 2023-02-02 12:41 ` [PATCH 03/39] target/riscv: Add vclmul.vx " Lawrence Hunter 2023-02-02 13:59 ` Philipp Tomsich 2023-02-02 12:41 ` [PATCH 04/39] target/riscv: Add vclmulh.vv " Lawrence Hunter 2023-02-02 14:03 ` Philipp Tomsich 2023-02-02 16:54 ` Richard Henderson 2023-02-02 12:41 ` [PATCH 05/39] target/riscv: Add vclmulh.vx " Lawrence Hunter 2023-02-02 12:41 ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Lawrence Hunter 2023-02-02 12:41 ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Lawrence Hunter 2023-02-02 14:13 ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Philipp Tomsich 2023-02-02 14:13 ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Philipp Tomsich 2023-02-02 14:30 ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Philipp Tomsich 2023-02-02 14:30 ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Philipp Tomsich 2023-02-02 17:35 ` Richard Henderson 2023-02-02 18:07 ` Philipp Tomsich 2023-02-02 23:14 ` Richard Henderson 2023-02-02 12:41 ` [PATCH 07/39] target/riscv: Add vbrev8.v " Lawrence Hunter 2023-02-02 14:21 ` Philipp Tomsich 2023-02-02 12:41 ` [PATCH 08/39] target/riscv: Add vrev8.v " Lawrence Hunter 2023-02-02 14:22 ` Philipp Tomsich 2023-02-02 12:42 ` Lawrence Hunter [this message] 2023-02-02 12:42 ` [PATCH 09/39] target/riscv: Add vandn.[vv, vx, vi] " Lawrence Hunter 2023-02-02 14:29 ` [PATCH 09/39] target/riscv: Add vandn.[vv,vx,vi] " Philipp Tomsich 2023-02-02 12:42 ` [PATCH 10/39] target/riscv: expose zvkb cpu property Lawrence Hunter 2023-02-02 14:23 ` Philipp Tomsich 2023-02-02 14:24 ` Philipp Tomsich 2023-02-02 12:42 ` [PATCH 11/39] target/riscv: add zvkns " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 12/39] target/riscv: Add vaesef.vv decoding, translation and execution support Lawrence Hunter 2023-02-02 12:42 ` [PATCH 13/39] target/riscv: Add vaesef.vs " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 14/39] target/riscv: Add vaesdf.vv " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 15/39] target/riscv: Add vaesdf.vs " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 16/39] target/riscv: Add vaesdm.vv " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 17/39] target/riscv: Add vaesdm.vs " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 18/39] target/riscv: Add vaesz.vs " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 19/39] target/riscv: Add vaesem.vv " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 20/39] target/riscv: Add vaesem.vs " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 21/39] target/riscv: Add vaeskf1.vi " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 22/39] target/riscv: Add vaeskf2.vi " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 23/39] target/riscv: expose zvkns cpu property Lawrence Hunter 2023-02-02 12:42 ` [PATCH 24/39] target/riscv: add zvknh cpu properties Lawrence Hunter 2023-02-02 12:42 ` [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support Lawrence Hunter 2023-02-02 12:42 ` [PATCH 26/39] target/riscv: Add vsha2c[hl].vv " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 27/39] target/riscv: expose zvknh cpu properties Lawrence Hunter 2023-02-02 12:42 ` [PATCH 28/39] target/riscv: add zvksh cpu property Lawrence Hunter 2023-02-02 12:42 ` [PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support Lawrence Hunter 2023-02-02 12:42 ` [PATCH 30/39] target/riscv: Add vsm3c.vi " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 31/39] target/riscv: expose zvksh cpu property Lawrence Hunter 2023-02-02 12:42 ` [PATCH 32/39] target/riscv: add zvkg " Lawrence Hunter 2023-02-02 12:42 ` [PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support Lawrence Hunter 2023-02-02 12:42 ` [PATCH 34/39] target/riscv: expose zvkg cpu property Lawrence Hunter 2023-02-02 12:42 ` [PATCH 35/39] crypto: Move SM4_SBOXWORD from target/riscv Lawrence Hunter 2023-02-02 17:02 ` Richard Henderson 2023-02-02 12:42 ` [PATCH 36/39] crypto: Add SM4 constant parameter CK Lawrence Hunter 2023-02-02 12:42 ` [PATCH 37/39] target/riscv: Add zvksed cfg property Lawrence Hunter 2023-02-02 12:42 ` [PATCH 38/39] target/riscv: Add Zvksed support Lawrence Hunter 2023-02-02 12:42 ` [PATCH 39/39] target/riscv: Expose Zvksed property Lawrence Hunter
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