From: Moudy Ho <moudy.ho@mediatek.com> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Matthias Brugger <matthias.bgg@gmail.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org> Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, Moudy Ho <moudy.ho@mediatek.com> Subject: [PATCH v7 3/6] arm64: dts: mediatek: mt8195: add MUTEX configuration for VPPSYS Date: Mon, 6 Feb 2023 17:11:06 +0800 [thread overview] Message-ID: <20230206091109.1324-4-moudy.ho@mediatek.com> (raw) In-Reply-To: <20230206091109.1324-1-moudy.ho@mediatek.com> In MT8195, the MMSYS has two Video Processor Pipepline Subsystems named VPPSYS0 and VPPSYS1, each with specific MUTEX to control Start of Frame(SOF) and End of Frame (EOF) signals. Before working with them, the addresses, interrupts, clocks and power domains need to be set up in dts. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 526136703142..8fc527570791 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1801,6 +1801,15 @@ #clock-cells = <1>; }; + mutex@1400f000 { + compatible = "mediatek,mt8195-vpp-mutex"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MUTEX>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { compatible = "mediatek,mt8195-smi-sub-common"; reg = <0 0x14010000 0 0x1000>; @@ -1906,6 +1915,15 @@ #clock-cells = <1>; }; + mutex@14f01000 { + compatible = "mediatek,mt8195-vpp-mutex"; + reg = <0 0x14f01000 0 0x1000>; + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + larb5: larb@14f02000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x14f02000 0 0x1000>; -- 2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Moudy Ho <moudy.ho@mediatek.com> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Matthias Brugger <matthias.bgg@gmail.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org> Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, Moudy Ho <moudy.ho@mediatek.com> Subject: [PATCH v7 3/6] arm64: dts: mediatek: mt8195: add MUTEX configuration for VPPSYS Date: Mon, 6 Feb 2023 17:11:06 +0800 [thread overview] Message-ID: <20230206091109.1324-4-moudy.ho@mediatek.com> (raw) In-Reply-To: <20230206091109.1324-1-moudy.ho@mediatek.com> In MT8195, the MMSYS has two Video Processor Pipepline Subsystems named VPPSYS0 and VPPSYS1, each with specific MUTEX to control Start of Frame(SOF) and End of Frame (EOF) signals. Before working with them, the addresses, interrupts, clocks and power domains need to be set up in dts. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 526136703142..8fc527570791 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1801,6 +1801,15 @@ #clock-cells = <1>; }; + mutex@1400f000 { + compatible = "mediatek,mt8195-vpp-mutex"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MUTEX>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { compatible = "mediatek,mt8195-smi-sub-common"; reg = <0 0x14010000 0 0x1000>; @@ -1906,6 +1915,15 @@ #clock-cells = <1>; }; + mutex@14f01000 { + compatible = "mediatek,mt8195-vpp-mutex"; + reg = <0 0x14f01000 0 0x1000>; + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + larb5: larb@14f02000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x14f02000 0 0x1000>; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-02-06 9:11 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-06 9:11 [PATCH v7 0/6] add support for MT8195 VPPSYS on MMSYS and MUTEX Moudy Ho 2023-02-06 9:11 ` Moudy Ho 2023-02-06 9:11 ` [PATCH v7 1/6] dt-bindings: soc: mediatek: Add support for MT8195 VPPSYS Moudy Ho 2023-02-06 9:11 ` Moudy Ho 2023-02-06 9:11 ` [PATCH v7 2/6] arm64: dts: mediatek: mt8195: add MMSYS configuration for VPPSYS Moudy Ho 2023-02-06 9:11 ` Moudy Ho 2023-02-06 11:12 ` Chen-Yu Tsai 2023-02-06 11:12 ` Chen-Yu Tsai 2023-02-06 9:11 ` Moudy Ho [this message] 2023-02-06 9:11 ` [PATCH v7 3/6] arm64: dts: mediatek: mt8195: add MUTEX " Moudy Ho 2023-02-06 11:14 ` Chen-Yu Tsai 2023-02-06 11:14 ` Chen-Yu Tsai 2023-02-06 9:11 ` [PATCH v7 4/6] soc: mediatek: mmsys: add config api for RSZ switching and DCM Moudy Ho 2023-02-06 9:11 ` Moudy Ho 2023-02-06 9:11 ` [PATCH v7 5/6] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1 Moudy Ho 2023-02-06 9:11 ` Moudy Ho 2023-02-06 11:17 ` Chen-Yu Tsai 2023-02-06 11:17 ` Chen-Yu Tsai 2023-02-06 9:11 ` [PATCH v7 6/6] soc: mediatek: mutex: support MT8195 VPPSYS Moudy Ho 2023-02-06 9:11 ` Moudy Ho 2023-02-06 18:23 ` [PATCH v7 0/6] add support for MT8195 VPPSYS on MMSYS and MUTEX Matthias Brugger 2023-02-06 18:23 ` Matthias Brugger
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