From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>
Subject: [PATCH v2 5/8] arm64: dts: qcom: sm8350: move more nodes to correct place
Date: Mon, 6 Feb 2023 16:57:04 +0200 [thread overview]
Message-ID: <20230206145707.122937-6-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org>
Continue ordering DT nodes. Move RNG, UFS, system NoC and SLPI nodes
to the proper position.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 314 +++++++++++++--------------
1 file changed, 157 insertions(+), 157 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 061aa3fec1c4..c327dc925793 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1423,6 +1423,13 @@ spi13: spi@a94000 {
};
};
+ rng: rng@10d3000 {
+ compatible = "qcom,prng-ee";
+ reg = <0 0x010d3000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_HWKM_CLK>;
+ clock-names = "core";
+ };
+
config_noc: interconnect@1500000 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x01500000 0 0xa580>;
@@ -1643,18 +1650,76 @@ pcie1_phy: phy@1c0f000 {
status = "disabled";
};
- lpass_ag_noc: interconnect@3c40000 {
- compatible = "qcom,sm8350-lpass-ag-noc";
- reg = <0 0x03c40000 0 0xf080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ iommus = <&apps_smmu 0xe0 0x0>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ status = "disabled";
};
- compute_noc: interconnect@a0c0000 {
- compatible = "qcom,sm8350-compute-noc";
- reg = <0 0x0a0c0000 0 0xa180>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sm8350-qmp-ufs-phy";
+ reg = <0 0x01d87000 0 0x1c4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "ref",
+ "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ status = "disabled";
+
+ ufs_mem_phy_lanes: phy@1d87400 {
+ reg = <0 0x01d87400 0 0x188>,
+ <0 0x01d87600 0 0x200>,
+ <0 0x01d87c00 0 0x200>,
+ <0 0x01d87800 0 0x188>,
+ <0 0x01d87a00 0 0x200>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
};
ipa: ipa@1e40000 {
@@ -1702,6 +1767,13 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ lpass_ag_noc: interconnect@3c40000 {
+ compatible = "qcom,sm8350-lpass-ag-noc";
+ reg = <0 0x03c40000 0 0xf080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
mpss: remoteproc@4080000 {
compatible = "qcom,sm8350-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
@@ -1744,6 +1816,74 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
+ slpi: remoteproc@5c00000 {
+ compatible = "qcom,sm8350-slpi-pas";
+ reg = <0 0x05c00000 0 0x4000>;
+
+ interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SM8350_LCX>,
+ <&rpmhpd SM8350_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&pil_slpi_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_slpi_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "slpi";
+ qcom,remote-pid = <3>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "sdsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0541 0x0>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0542 0x0>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0543 0x0>;
+ /* note: shared-cb = <4> in downstream */
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
@@ -2014,153 +2154,6 @@ qup_i2c19_default: qup-i2c19-default-state {
};
};
- rng: rng@10d3000 {
- compatible = "qcom,prng-ee";
- reg = <0 0x010d3000 0 0x1000>;
- clocks = <&rpmhcc RPMH_HWKM_CLK>;
- clock-names = "core";
- };
-
- ufs_mem_hc: ufshc@1d84000 {
- compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
- "jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>;
- interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
- phy-names = "ufsphy";
- lanes-per-direction = <2>;
- #reset-cells = <1>;
- resets = <&gcc GCC_UFS_PHY_BCR>;
- reset-names = "rst";
-
- power-domains = <&gcc UFS_PHY_GDSC>;
-
- iommus = <&apps_smmu 0xe0 0x0>;
-
- clock-names =
- "core_clk",
- "bus_aggr_clk",
- "iface_clk",
- "core_clk_unipro",
- "ref_clk",
- "tx_lane0_sync_clk",
- "rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
- clocks =
- <&gcc GCC_UFS_PHY_AXI_CLK>,
- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
- <&gcc GCC_UFS_PHY_AHB_CLK>,
- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
- status = "disabled";
- };
-
- ufs_mem_phy: phy@1d87000 {
- compatible = "qcom,sm8350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-
- resets = <&ufs_mem_hc 0>;
- reset-names = "ufsphy";
- status = "disabled";
-
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
- };
-
- slpi: remoteproc@5c00000 {
- compatible = "qcom,sm8350-slpi-pas";
- reg = <0 0x05c00000 0 0x4000>;
-
- interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
- <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready",
- "handover", "stop-ack";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd SM8350_LCX>,
- <&rpmhpd SM8350_LMX>;
- power-domain-names = "lcx", "lmx";
-
- memory-region = <&pil_slpi_mem>;
-
- qcom,qmp = <&aoss_qmp>;
-
- qcom,smem-states = <&smp2p_slpi_out 0>;
- qcom,smem-state-names = "stop";
-
- status = "disabled";
-
- glink-edge {
- interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_CLIENT_SLPI
- IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
- label = "slpi";
- qcom,remote-pid = <3>;
-
- fastrpc {
- compatible = "qcom,fastrpc";
- qcom,glink-channels = "fastrpcglink-apps-dsp";
- label = "sdsp";
- qcom,non-secure-domain;
- #address-cells = <1>;
- #size-cells = <0>;
-
- compute-cb@1 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <1>;
- iommus = <&apps_smmu 0x0541 0x0>;
- };
-
- compute-cb@2 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <2>;
- iommus = <&apps_smmu 0x0542 0x0>;
- };
-
- compute-cb@3 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <3>;
- iommus = <&apps_smmu 0x0543 0x0>;
- /* note: shared-cb = <4> in downstream */
- };
- };
- };
- };
-
sdhc_2: mmc@8804000 {
compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -2309,6 +2302,13 @@ system-cache-controller@9200000 {
reg-names = "llcc_base", "llcc_broadcast_base";
};
+ compute_noc: interconnect@a0c0000 {
+ compatible = "qcom,sm8350-compute-noc";
+ reg = <0 0x0a0c0000 0 0xa180>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
--
2.39.1
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
Sean Paul <sean@poorly.run>,
linux-clk@vger.kernel.org
Subject: [PATCH v2 5/8] arm64: dts: qcom: sm8350: move more nodes to correct place
Date: Mon, 6 Feb 2023 16:57:04 +0200 [thread overview]
Message-ID: <20230206145707.122937-6-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org>
Continue ordering DT nodes. Move RNG, UFS, system NoC and SLPI nodes
to the proper position.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 314 +++++++++++++--------------
1 file changed, 157 insertions(+), 157 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 061aa3fec1c4..c327dc925793 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1423,6 +1423,13 @@ spi13: spi@a94000 {
};
};
+ rng: rng@10d3000 {
+ compatible = "qcom,prng-ee";
+ reg = <0 0x010d3000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_HWKM_CLK>;
+ clock-names = "core";
+ };
+
config_noc: interconnect@1500000 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x01500000 0 0xa580>;
@@ -1643,18 +1650,76 @@ pcie1_phy: phy@1c0f000 {
status = "disabled";
};
- lpass_ag_noc: interconnect@3c40000 {
- compatible = "qcom,sm8350-lpass-ag-noc";
- reg = <0 0x03c40000 0 0xf080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ iommus = <&apps_smmu 0xe0 0x0>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ status = "disabled";
};
- compute_noc: interconnect@a0c0000 {
- compatible = "qcom,sm8350-compute-noc";
- reg = <0 0x0a0c0000 0 0xa180>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sm8350-qmp-ufs-phy";
+ reg = <0 0x01d87000 0 0x1c4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "ref",
+ "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ status = "disabled";
+
+ ufs_mem_phy_lanes: phy@1d87400 {
+ reg = <0 0x01d87400 0 0x188>,
+ <0 0x01d87600 0 0x200>,
+ <0 0x01d87c00 0 0x200>,
+ <0 0x01d87800 0 0x188>,
+ <0 0x01d87a00 0 0x200>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
};
ipa: ipa@1e40000 {
@@ -1702,6 +1767,13 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ lpass_ag_noc: interconnect@3c40000 {
+ compatible = "qcom,sm8350-lpass-ag-noc";
+ reg = <0 0x03c40000 0 0xf080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
mpss: remoteproc@4080000 {
compatible = "qcom,sm8350-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
@@ -1744,6 +1816,74 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
+ slpi: remoteproc@5c00000 {
+ compatible = "qcom,sm8350-slpi-pas";
+ reg = <0 0x05c00000 0 0x4000>;
+
+ interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SM8350_LCX>,
+ <&rpmhpd SM8350_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&pil_slpi_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_slpi_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "slpi";
+ qcom,remote-pid = <3>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "sdsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0541 0x0>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0542 0x0>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0543 0x0>;
+ /* note: shared-cb = <4> in downstream */
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
@@ -2014,153 +2154,6 @@ qup_i2c19_default: qup-i2c19-default-state {
};
};
- rng: rng@10d3000 {
- compatible = "qcom,prng-ee";
- reg = <0 0x010d3000 0 0x1000>;
- clocks = <&rpmhcc RPMH_HWKM_CLK>;
- clock-names = "core";
- };
-
- ufs_mem_hc: ufshc@1d84000 {
- compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
- "jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>;
- interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
- phy-names = "ufsphy";
- lanes-per-direction = <2>;
- #reset-cells = <1>;
- resets = <&gcc GCC_UFS_PHY_BCR>;
- reset-names = "rst";
-
- power-domains = <&gcc UFS_PHY_GDSC>;
-
- iommus = <&apps_smmu 0xe0 0x0>;
-
- clock-names =
- "core_clk",
- "bus_aggr_clk",
- "iface_clk",
- "core_clk_unipro",
- "ref_clk",
- "tx_lane0_sync_clk",
- "rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
- clocks =
- <&gcc GCC_UFS_PHY_AXI_CLK>,
- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
- <&gcc GCC_UFS_PHY_AHB_CLK>,
- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
- status = "disabled";
- };
-
- ufs_mem_phy: phy@1d87000 {
- compatible = "qcom,sm8350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-
- resets = <&ufs_mem_hc 0>;
- reset-names = "ufsphy";
- status = "disabled";
-
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
- };
-
- slpi: remoteproc@5c00000 {
- compatible = "qcom,sm8350-slpi-pas";
- reg = <0 0x05c00000 0 0x4000>;
-
- interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
- <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready",
- "handover", "stop-ack";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd SM8350_LCX>,
- <&rpmhpd SM8350_LMX>;
- power-domain-names = "lcx", "lmx";
-
- memory-region = <&pil_slpi_mem>;
-
- qcom,qmp = <&aoss_qmp>;
-
- qcom,smem-states = <&smp2p_slpi_out 0>;
- qcom,smem-state-names = "stop";
-
- status = "disabled";
-
- glink-edge {
- interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_CLIENT_SLPI
- IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
- label = "slpi";
- qcom,remote-pid = <3>;
-
- fastrpc {
- compatible = "qcom,fastrpc";
- qcom,glink-channels = "fastrpcglink-apps-dsp";
- label = "sdsp";
- qcom,non-secure-domain;
- #address-cells = <1>;
- #size-cells = <0>;
-
- compute-cb@1 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <1>;
- iommus = <&apps_smmu 0x0541 0x0>;
- };
-
- compute-cb@2 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <2>;
- iommus = <&apps_smmu 0x0542 0x0>;
- };
-
- compute-cb@3 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <3>;
- iommus = <&apps_smmu 0x0543 0x0>;
- /* note: shared-cb = <4> in downstream */
- };
- };
- };
- };
-
sdhc_2: mmc@8804000 {
compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -2309,6 +2302,13 @@ system-cache-controller@9200000 {
reg-names = "llcc_base", "llcc_broadcast_base";
};
+ compute_noc: interconnect@a0c0000 {
+ compatible = "qcom,sm8350-compute-noc";
+ reg = <0 0x0a0c0000 0 0xa180>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
--
2.39.1
next prev parent reply other threads:[~2023-02-06 14:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 14:56 [PATCH v2 0/8] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
2023-02-06 14:56 ` Dmitry Baryshkov
2023-02-06 14:57 ` [PATCH v2 1/8] dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml Dmitry Baryshkov
2023-02-06 14:57 ` [PATCH v2 1/8] dt-bindings: clock: Merge qcom, gpucc-sm8350 into qcom, gpucc.yaml Dmitry Baryshkov
2023-02-07 20:40 ` [PATCH v2 1/8] dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml Rob Herring
2023-02-07 20:40 ` Rob Herring
2023-02-06 14:57 ` [PATCH v2 2/8] dt-bindings: power: qcom,rpmpd: add RPMH_REGULATOR_LEVEL_LOW_SVS_L1 Dmitry Baryshkov
2023-02-06 14:57 ` [PATCH v2 2/8] dt-bindings: power: qcom, rpmpd: " Dmitry Baryshkov
2023-02-06 20:19 ` [PATCH v2 2/8] dt-bindings: power: qcom,rpmpd: " Konrad Dybcio
2023-02-06 20:19 ` Konrad Dybcio
2023-02-06 14:57 ` [PATCH v2 3/8] dt-bindings: display/msm/gmu: add Adreno 660 support Dmitry Baryshkov
2023-02-06 14:57 ` Dmitry Baryshkov
2023-02-07 20:41 ` Rob Herring
2023-02-07 20:41 ` Rob Herring
2023-02-06 14:57 ` [PATCH v2 4/8] arm64: dts: qcom: sm8350: reorder device nodes Dmitry Baryshkov
2023-02-06 14:57 ` Dmitry Baryshkov
2023-02-08 9:22 ` Konrad Dybcio
2023-02-08 9:22 ` Konrad Dybcio
2023-02-09 3:28 ` Bjorn Andersson
2023-02-09 3:28 ` Bjorn Andersson
2023-02-09 13:40 ` Dmitry Baryshkov
2023-02-09 13:40 ` Dmitry Baryshkov
2023-02-06 14:57 ` Dmitry Baryshkov [this message]
2023-02-06 14:57 ` [PATCH v2 5/8] arm64: dts: qcom: sm8350: move more nodes to correct place Dmitry Baryshkov
2023-02-06 14:57 ` [PATCH v2 6/8] arm64: dts: qcom: sm8350: finish reordering nodes Dmitry Baryshkov
2023-02-06 14:57 ` Dmitry Baryshkov
2023-02-06 14:57 ` [PATCH v2 7/8] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes Dmitry Baryshkov
2023-02-06 14:57 ` Dmitry Baryshkov
2023-02-06 14:57 ` [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable GPU Dmitry Baryshkov
2023-02-06 14:57 ` Dmitry Baryshkov
2023-02-08 16:43 ` Konrad Dybcio
2023-02-08 16:43 ` Konrad Dybcio
2023-02-09 4:22 ` (subset) [PATCH v2 0/8] arm64: dts: qcom: sm8350: enable GPU on the HDK board Bjorn Andersson
2023-02-09 4:22 ` Bjorn Andersson
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