From: Tinghan Shen <tinghan.shen@mediatek.com>
To: Bjorn Andersson <andersson@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Tinghan Shen <tinghan.shen@mediatek.com>
Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v4 04/12] remoteproc: mediatek: Add SCP core 1 register definitions
Date: Thu, 9 Feb 2023 15:40:13 +0800 [thread overview]
Message-ID: <20230209074021.13936-5-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20230209074021.13936-1-tinghan.shen@mediatek.com>
Add MT8195 SCP core 1 related register definitions.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index ea6fa1100a00..3778894c96f3 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -47,6 +47,7 @@
#define MT8192_SCP2SPM_IPC_CLR 0x4094
#define MT8192_GIPC_IN_SET 0x4098
#define MT8192_HOST_IPC_INT_BIT BIT(0)
+#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4)
#define MT8192_CORE0_SW_RSTN_CLR 0x10000
#define MT8192_CORE0_SW_RSTN_SET 0x10004
@@ -56,6 +57,26 @@
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
+#define MT8195_CPU1_SRAM_PD 0x1084
+#define MT8195_SSHUB2APMCU_IPC_SET 0x4088
+#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C
+#define MT8195_CORE1_SW_RSTN_CLR 0x20000
+#define MT8195_CORE1_SW_RSTN_SET 0x20004
+#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
+#define MT8195_CORE1_WDT_IRQ 0x20030
+#define MT8195_CORE1_WDT_CFG 0x20034
+
+#define MT8195_SEC_CTRL 0x85000
+#define MT8195_CORE_OFFSET_ENABLE_D BIT(13)
+#define MT8195_CORE_OFFSET_ENABLE_I BIT(12)
+#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0
+#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4
+#define MT8195_L2TCM_OFFSET 0x850d0
+#define SCP_SRAM_REMAP_LOW 0
+#define SCP_SRAM_REMAP_HIGH 1
+#define SCP_SRAM_REMAP_OFFSET 2
+#define SCP_SRAM_REMAP_SIZE 3
+
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Tinghan Shen <tinghan.shen@mediatek.com>
To: Bjorn Andersson <andersson@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Tinghan Shen <tinghan.shen@mediatek.com>
Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v4 04/12] remoteproc: mediatek: Add SCP core 1 register definitions
Date: Thu, 9 Feb 2023 15:40:13 +0800 [thread overview]
Message-ID: <20230209074021.13936-5-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20230209074021.13936-1-tinghan.shen@mediatek.com>
Add MT8195 SCP core 1 related register definitions.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index ea6fa1100a00..3778894c96f3 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -47,6 +47,7 @@
#define MT8192_SCP2SPM_IPC_CLR 0x4094
#define MT8192_GIPC_IN_SET 0x4098
#define MT8192_HOST_IPC_INT_BIT BIT(0)
+#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4)
#define MT8192_CORE0_SW_RSTN_CLR 0x10000
#define MT8192_CORE0_SW_RSTN_SET 0x10004
@@ -56,6 +57,26 @@
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
+#define MT8195_CPU1_SRAM_PD 0x1084
+#define MT8195_SSHUB2APMCU_IPC_SET 0x4088
+#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C
+#define MT8195_CORE1_SW_RSTN_CLR 0x20000
+#define MT8195_CORE1_SW_RSTN_SET 0x20004
+#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
+#define MT8195_CORE1_WDT_IRQ 0x20030
+#define MT8195_CORE1_WDT_CFG 0x20034
+
+#define MT8195_SEC_CTRL 0x85000
+#define MT8195_CORE_OFFSET_ENABLE_D BIT(13)
+#define MT8195_CORE_OFFSET_ENABLE_I BIT(12)
+#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0
+#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4
+#define MT8195_L2TCM_OFFSET 0x850d0
+#define SCP_SRAM_REMAP_LOW 0
+#define SCP_SRAM_REMAP_HIGH 1
+#define SCP_SRAM_REMAP_OFFSET 2
+#define SCP_SRAM_REMAP_SIZE 3
+
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288
--
2.18.0
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next prev parent reply other threads:[~2023-02-09 7:41 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-09 7:40 [PATCH v4 00/12] Add support for MT8195 SCP 2nd core Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 7:40 ` [PATCH v4 01/12] dt-bindings: remoteproc: mediatek: Improve the rpmsg subnode definition Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 19:02 ` Rob Herring
2023-02-09 19:02 ` Rob Herring
2023-02-09 7:40 ` [PATCH v4 02/12] arm64: dts: mediatek: mt8183-kukui: Update the node name of SCP rpmsg subnode Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 7:40 ` [PATCH v4 03/12] dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 19:05 ` Rob Herring
2023-02-09 19:05 ` Rob Herring
2023-02-09 7:40 ` Tinghan Shen [this message]
2023-02-09 7:40 ` [PATCH v4 04/12] remoteproc: mediatek: Add SCP core 1 register definitions Tinghan Shen
2023-02-09 7:40 ` [PATCH v4 05/12] remoteproc: mediatek: Add MT8195 SCP core 1 operations Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 7:40 ` [PATCH v4 06/12] remoteproc: mediatek: Extract remoteproc initialization flow Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 12:43 ` AngeloGioacchino Del Regno
2023-02-09 12:43 ` AngeloGioacchino Del Regno
2023-02-09 7:40 ` [PATCH v4 07/12] remoteproc: mediatek: Probe multi-core SCP Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 12:41 ` AngeloGioacchino Del Regno
2023-02-09 12:41 ` AngeloGioacchino Del Regno
2023-02-09 7:40 ` [PATCH v4 08/12] remoteproc: mediatek: Control SCP core 1 by rproc subdevice Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 7:40 ` [PATCH v4 09/12] remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 7:40 ` [PATCH v4 10/12] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 12:48 ` AngeloGioacchino Del Regno
2023-02-09 12:48 ` AngeloGioacchino Del Regno
2023-02-10 3:24 ` TingHan Shen (沈廷翰)
2023-02-10 3:24 ` TingHan Shen (沈廷翰)
2023-02-09 7:40 ` [PATCH v4 11/12] remoteproc: mediatek: Refine ipi handler error message Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
2023-02-09 7:40 ` [PATCH v4 12/12] arm64: dts: mediatek: mt8195: Add SCP 2nd core Tinghan Shen
2023-02-09 7:40 ` Tinghan Shen
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