From: Evan Green <evan@rivosinc.com> To: Palmer Dabbelt <palmer@rivosinc.com> Cc: heiko@sntech.de, Conor Dooley <conor@kernel.org>, slewis@rivosinc.com, vineetg@rivosinc.com, Evan Green <evan@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Andrew Bresticker <abrestic@rivosinc.com>, Atish Patra <atishp@rivosinc.com>, Celeste Liu <coelacanthus@outlook.com>, Guo Ren <guoren@kernel.org>, Jonathan Corbet <corbet@lwn.net>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/7] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Tue, 21 Feb 2023 11:08:54 -0800 [thread overview] Message-ID: <20230221190858.3159617-4-evan@rivosinc.com> (raw) In-Reply-To: <20230221190858.3159617-1-evan@rivosinc.com> We have an implicit set of base behaviors that userspace depends on, which are mostly defined in various ISA specifications. Co-developed-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Evan Green <evan@rivosinc.com> --- Changes in v3: - Refactored base ISA behavior probe to allow kernel probing as well, in prep for vDSO data initialization. - Fixed doc warnings in IMA text list, use :c:macro:. Documentation/riscv/hwprobe.rst | 21 +++++++++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_riscv.c | 20 ++++++++++++++++++++ 4 files changed, 47 insertions(+), 1 deletion(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 88b015a2026e..9f2da414fbf8 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -37,3 +37,24 @@ The following keys are defined: defined by the RISC-V privileged architecture specification. * :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as defined by the RISC-V privileged architecture specification. +* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base + user-visible behavior that this kernel supports. The following base user ABIs + are defined: + + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or + rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the + privileged ISA, with the following known exceptions (more exceptions may be + added, but only if it can be demonstrated that the user ABI is not broken): + + * The :fence.i: instruction cannot be directly executed by userspace + programs (it may still be executed in userspace via a + kernel-controlled mechanism such as the vDSO). +* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: + base system behavior. + + * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as + defined by commit cd20cee ("FMIN/FMAX now implement + minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined + by version 2.2 of the RISC-V ISA manual. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 08d1c3bdd78a..7e52f1e1fe10 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include <uapi/asm/hwprobe.h> -#define RISCV_HWPROBE_MAX_KEY 2 +#define RISCV_HWPROBE_MAX_KEY 4 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 591802047460..fc5665411782 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -20,6 +20,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MVENDORID 0 #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 02c2f1f7417e..f2b224550923 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -9,6 +9,7 @@ #include <asm/cacheflush.h> #include <asm/hwprobe.h> #include <asm/sbi.h> +#include <asm/switch_to.h> #include <asm/uaccess.h> #include <asm/unistd.h> #include <asm-generic/mman-common.h> @@ -124,6 +125,25 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, case RISCV_HWPROBE_KEY_MIMPID: hwprobe_arch_id(pair, cpus); break; + /* + * The kernel already assumes that the base single-letter ISA + * extensions are supported on all harts, and only supports the + * IMA base, so just cheat a bit here and tell that to + * userspace. + */ + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; + break; + + case RISCV_HWPROBE_KEY_IMA_EXT_0: + pair->value = 0; + if (has_fpu()) + pair->value |= RISCV_HWPROBE_IMA_FD; + + if (elf_hwcap & RISCV_ISA_EXT_c) + pair->value |= RISCV_HWPROBE_IMA_C; + + break; /* * For forward compatibility, unknown keys don't fail the whole -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Evan Green <evan@rivosinc.com> To: Palmer Dabbelt <palmer@rivosinc.com> Cc: heiko@sntech.de, Conor Dooley <conor@kernel.org>, slewis@rivosinc.com, vineetg@rivosinc.com, Evan Green <evan@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Andrew Bresticker <abrestic@rivosinc.com>, Atish Patra <atishp@rivosinc.com>, Celeste Liu <coelacanthus@outlook.com>, Guo Ren <guoren@kernel.org>, Jonathan Corbet <corbet@lwn.net>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/7] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Tue, 21 Feb 2023 11:08:54 -0800 [thread overview] Message-ID: <20230221190858.3159617-4-evan@rivosinc.com> (raw) In-Reply-To: <20230221190858.3159617-1-evan@rivosinc.com> We have an implicit set of base behaviors that userspace depends on, which are mostly defined in various ISA specifications. Co-developed-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Evan Green <evan@rivosinc.com> --- Changes in v3: - Refactored base ISA behavior probe to allow kernel probing as well, in prep for vDSO data initialization. - Fixed doc warnings in IMA text list, use :c:macro:. Documentation/riscv/hwprobe.rst | 21 +++++++++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_riscv.c | 20 ++++++++++++++++++++ 4 files changed, 47 insertions(+), 1 deletion(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 88b015a2026e..9f2da414fbf8 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -37,3 +37,24 @@ The following keys are defined: defined by the RISC-V privileged architecture specification. * :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as defined by the RISC-V privileged architecture specification. +* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base + user-visible behavior that this kernel supports. The following base user ABIs + are defined: + + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or + rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the + privileged ISA, with the following known exceptions (more exceptions may be + added, but only if it can be demonstrated that the user ABI is not broken): + + * The :fence.i: instruction cannot be directly executed by userspace + programs (it may still be executed in userspace via a + kernel-controlled mechanism such as the vDSO). +* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: + base system behavior. + + * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as + defined by commit cd20cee ("FMIN/FMAX now implement + minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined + by version 2.2 of the RISC-V ISA manual. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 08d1c3bdd78a..7e52f1e1fe10 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include <uapi/asm/hwprobe.h> -#define RISCV_HWPROBE_MAX_KEY 2 +#define RISCV_HWPROBE_MAX_KEY 4 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 591802047460..fc5665411782 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -20,6 +20,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MVENDORID 0 #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 02c2f1f7417e..f2b224550923 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -9,6 +9,7 @@ #include <asm/cacheflush.h> #include <asm/hwprobe.h> #include <asm/sbi.h> +#include <asm/switch_to.h> #include <asm/uaccess.h> #include <asm/unistd.h> #include <asm-generic/mman-common.h> @@ -124,6 +125,25 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, case RISCV_HWPROBE_KEY_MIMPID: hwprobe_arch_id(pair, cpus); break; + /* + * The kernel already assumes that the base single-letter ISA + * extensions are supported on all harts, and only supports the + * IMA base, so just cheat a bit here and tell that to + * userspace. + */ + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; + break; + + case RISCV_HWPROBE_KEY_IMA_EXT_0: + pair->value = 0; + if (has_fpu()) + pair->value |= RISCV_HWPROBE_IMA_FD; + + if (elf_hwcap & RISCV_ISA_EXT_c) + pair->value |= RISCV_HWPROBE_IMA_C; + + break; /* * For forward compatibility, unknown keys don't fail the whole -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-21 19:09 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-21 19:08 [PATCH v3 0/7] RISC-V Hardware Probing User Interface Evan Green 2023-02-21 19:08 ` Evan Green 2023-02-21 19:08 ` [PATCH v3 1/7] RISC-V: Move struct riscv_cpuinfo to new header Evan Green 2023-02-21 19:08 ` Evan Green 2023-02-21 19:08 ` [PATCH v3 2/7] RISC-V: Add a syscall for HW probing Evan Green 2023-02-21 19:08 ` Evan Green 2023-02-23 10:06 ` Arnd Bergmann 2023-02-23 10:06 ` Arnd Bergmann 2023-03-30 18:30 ` Evan Green 2023-03-30 18:30 ` Evan Green 2023-03-30 20:20 ` Heiko Stübner 2023-03-30 20:20 ` Heiko Stübner 2023-03-30 21:24 ` Evan Green 2023-03-30 21:24 ` Evan Green 2023-03-31 13:21 ` Arnd Bergmann 2023-03-31 13:21 ` Arnd Bergmann 2023-03-31 17:51 ` Evan Green 2023-03-31 17:51 ` Evan Green 2023-02-27 22:19 ` Conor Dooley 2023-02-27 22:19 ` Conor Dooley 2023-02-21 19:08 ` Evan Green [this message] 2023-02-21 19:08 ` [PATCH v3 3/7] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Evan Green 2023-02-27 22:47 ` Conor Dooley 2023-02-27 22:47 ` Conor Dooley 2023-03-03 0:56 ` Evan Green 2023-03-03 0:56 ` Evan Green 2023-02-21 19:08 ` [PATCH v3 4/7] dt-bindings: Add RISC-V misaligned access performance Evan Green 2023-02-21 19:08 ` Evan Green 2023-02-27 22:57 ` Conor Dooley 2023-02-27 22:57 ` Conor Dooley 2023-02-28 14:57 ` Rob Herring 2023-02-28 14:57 ` Rob Herring 2023-02-21 19:08 ` [PATCH v3 5/7] RISC-V: hwprobe: Support probing of " Evan Green 2023-02-21 19:08 ` Evan Green 2023-02-22 9:39 ` Joe Perches 2023-02-22 9:39 ` Joe Perches 2023-02-27 23:14 ` Conor Dooley 2023-02-27 23:14 ` Conor Dooley 2023-02-21 19:08 ` [PATCH v3 6/7] selftests: Test the new RISC-V hwprobe interface Evan Green 2023-02-21 19:08 ` Evan Green 2023-02-21 22:45 ` Mark Brown 2023-02-21 22:45 ` Mark Brown 2023-02-21 19:08 ` [PATCH v3 7/7] RISC-V: Add hwprobe vDSO function and data Evan Green 2023-02-21 19:08 ` Evan Green 2023-02-21 21:17 ` kernel test robot 2023-02-21 21:17 ` kernel test robot 2023-02-22 6:55 ` kernel test robot 2023-02-22 6:55 ` kernel test robot
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