[PATCH 0/4] Renesas r9a06g032 clock table improvements

From: Ralph Siemsen <ralph.siemsen@linaro.org>
To: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org
Cc: "Stephen Boyd" <sboyd@kernel.org>,
	"Miquèl Raynal" <miquel.raynal@bootlin.com>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Ralph Siemsen" <ralph.siemsen@linaro.org>
Subject: [PATCH 0/4] Renesas r9a06g032 clock table improvements
Date: Mon, 27 Feb 2023 13:39:32 -0500	[thread overview]
Message-ID: <20230227183937.377612-1-ralph.siemsen@linaro.org> (raw)

This patch series makes several mostly-cosmetic changes to improve the clock
tables for the r9a06g032 (RZ/N1). They could all be squashed into a single
commit, though I kept them separate to make review easier.

The motivation for this change is to make the register/bit numbers more
explicit in the clock tables. With the existing format, these values are packed
into a u16 value, which is difficult to understand. After this patch, the
memory format remains the same, but the tables now list the register and bit
numbers explicitly. The logic which accesses these has also been made a
bit simpler to understand.

Ralph Siemsen (4):
  clk: renesas: r9a06g032: improve readability
  clk: renesas: r9a06g032: drop unused fields
  clk: renesas: r9a06g032: document structs
  clk: renesas: r9a06g032: improve clock tables

 drivers/clk/renesas/r9a06g032-clocks.c | 726 ++++++++++++++++++-------
 1 file changed, 530 insertions(+), 196 deletions(-)

-- 
2.25.1