[PATCH v1 1/3] dt-bindings: PCI: brcmstb: Add two optional props

From: Jim Quinlan <jim2101024@gmail.com>
To: linux-pci@vger.kernel.org,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Cyril Brulebois <kibi@debian.org>,
	Phil Elwell <phil@raspberrypi.com>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
	james.quinlan@broadcom.com
Cc: "Florian Fainelli" <f.fainelli@gmail.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
	FLATTENED DEVICE TREE BINDINGS),
	linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v1 1/3] dt-bindings: PCI: brcmstb: Add two optional props
Date: Thu,  6 Apr 2023 08:46:22 -0400	[thread overview]
Message-ID: <20230406124625.41325-2-jim2101024@gmail.com> (raw)
In-Reply-To: <20230406124625.41325-1-jim2101024@gmail.com>

Regarding "brcm,enable-l1ss":

  The Broadcom STB/CM PCIe HW -- which is also used by RPi SOCs -- requires
  the driver probe to configure one of three clkreq# modes:

  (a) clkreq# driven by the RC
  (b) clkreq# driven by the EP for ASPM L0s, L1
  (c) bidirectional clkreq#, as used for L1 Substates (L1SS).

  The HW can tell the difference between (a) and (b), but does not know
  when to configure (c).  Further, the HW will cause a CPU abort on boot if
  guesses wrong regarding the need for (c).  So we introduce the boolean
  "brcm,enable-l1ss" property to indicate that (c) is desired.  This
  property is already present in the Raspian version of Linux, but the
  driver implementaion that will follow adds more details and discerns
  between (a) and (b).

Regarding "brcm,completion-timeout-msecs"

  Our HW will cause a CPU abort if the L1SS exit time is longer than the
  completion abort timeout.  We've been asked to make this configurable, so
  we are introducing "brcm,completion-abort-msecs".

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 .../devicetree/bindings/pci/brcm,stb-pcie.yaml       | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 7e15aae7d69e..ef4ccc05b258 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -64,6 +64,18 @@ properties:
 
   aspm-no-l0s: true
 
+  brcm,enable-l1ss:
+    description: Indicates that the downstream device is L1SS
+      capable and L1SS is desired, e.g. by setting
+      CONFIG_PCIEASPM_POWER_SUPERSAVE=y.  Note that CLKREQ#
+      assertion to clock active must be within 400ns.
+    type: boolean
+
+  brcm,completion-timeout-msecs:
+    description: Number of msecs before completion timeout
+      abort occurs.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
   brcm,scb-sizes:
     description: u64 giving the 64bit PCIe memory
       viewport size of a memory controller.  There may be up to
-- 
2.17.1

