From: Rob Herring <robh@kernel.org> To: Brad Larson <blarson@amd.com> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v13 08/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Tue, 11 Apr 2023 08:55:18 -0500 [thread overview] Message-ID: <20230411135518.GA2952600-robh@kernel.org> (raw) In-Reply-To: <20230410184526.15990-9-blarson@amd.com> On Mon, Apr 10, 2023 at 11:45:19AM -0700, Brad Larson wrote: > Add AMD Pensando common and Elba SoC specific device nodes > > Signed-off-by: Brad Larson <blarson@amd.com> > --- > > v11 changes: > - Delete reset-names > - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' > > v9 changes: > - Single node for spi0 system-controller and squash > the reset-controller child into parent Have you run this thru 'make dtbs_check'? I see at least one issue that should report. > --- > arch/arm64/boot/dts/amd/Makefile | 1 + > arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ > arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++++++ > arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ > arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ > arch/arm64/boot/dts/amd/elba.dtsi | 191 ++++++++++++++++++ > 6 files changed, 595 insertions(+) > create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts > create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi > > diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile > index 68103a8b0ef5..8502cc2afbc5 100644 > --- a/arch/arm64/boot/dts/amd/Makefile > +++ b/arch/arm64/boot/dts/amd/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb > dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb > diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi > new file mode 100644 > index 000000000000..37aadd442db8 > --- /dev/null > +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi > @@ -0,0 +1,189 @@ > +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > +/* > + * Copyright 2020-2022 Advanced Micro Devices, Inc. > + */ > + > +/ { > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { cpu = <&cpu0>; }; > + core1 { cpu = <&cpu1>; }; > + core2 { cpu = <&cpu2>; }; > + core3 { cpu = <&cpu3>; }; > + }; > + > + cluster1 { > + core0 { cpu = <&cpu4>; }; > + core1 { cpu = <&cpu5>; }; > + core2 { cpu = <&cpu6>; }; > + core3 { cpu = <&cpu7>; }; > + }; > + > + cluster2 { > + core0 { cpu = <&cpu8>; }; > + core1 { cpu = <&cpu9>; }; > + core2 { cpu = <&cpu10>; }; > + core3 { cpu = <&cpu11>; }; > + }; > + > + cluster3 { > + core0 { cpu = <&cpu12>; }; > + core1 { cpu = <&cpu13>; }; > + core2 { cpu = <&cpu14>; }; > + core3 { cpu = <&cpu15>; }; > + }; > + }; > + > + /* CLUSTER 0 */ > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x0>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x1>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x2>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x3>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + l2_0: l2-cache0 { > + compatible = "cache"; > + }; > + > + /* CLUSTER 1 */ > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x100>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x101>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x102>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x103>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + l2_1: l2-cache1 { > + compatible = "cache"; This is missing properties. If you don't see warnings, update dtschema. Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org> To: Brad Larson <blarson@amd.com> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v13 08/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Tue, 11 Apr 2023 08:55:18 -0500 [thread overview] Message-ID: <20230411135518.GA2952600-robh@kernel.org> (raw) In-Reply-To: <20230410184526.15990-9-blarson@amd.com> On Mon, Apr 10, 2023 at 11:45:19AM -0700, Brad Larson wrote: > Add AMD Pensando common and Elba SoC specific device nodes > > Signed-off-by: Brad Larson <blarson@amd.com> > --- > > v11 changes: > - Delete reset-names > - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' > > v9 changes: > - Single node for spi0 system-controller and squash > the reset-controller child into parent Have you run this thru 'make dtbs_check'? I see at least one issue that should report. > --- > arch/arm64/boot/dts/amd/Makefile | 1 + > arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ > arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++++++ > arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ > arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ > arch/arm64/boot/dts/amd/elba.dtsi | 191 ++++++++++++++++++ > 6 files changed, 595 insertions(+) > create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts > create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi > create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi > > diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile > index 68103a8b0ef5..8502cc2afbc5 100644 > --- a/arch/arm64/boot/dts/amd/Makefile > +++ b/arch/arm64/boot/dts/amd/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb > dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb > diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi > new file mode 100644 > index 000000000000..37aadd442db8 > --- /dev/null > +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi > @@ -0,0 +1,189 @@ > +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > +/* > + * Copyright 2020-2022 Advanced Micro Devices, Inc. > + */ > + > +/ { > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { cpu = <&cpu0>; }; > + core1 { cpu = <&cpu1>; }; > + core2 { cpu = <&cpu2>; }; > + core3 { cpu = <&cpu3>; }; > + }; > + > + cluster1 { > + core0 { cpu = <&cpu4>; }; > + core1 { cpu = <&cpu5>; }; > + core2 { cpu = <&cpu6>; }; > + core3 { cpu = <&cpu7>; }; > + }; > + > + cluster2 { > + core0 { cpu = <&cpu8>; }; > + core1 { cpu = <&cpu9>; }; > + core2 { cpu = <&cpu10>; }; > + core3 { cpu = <&cpu11>; }; > + }; > + > + cluster3 { > + core0 { cpu = <&cpu12>; }; > + core1 { cpu = <&cpu13>; }; > + core2 { cpu = <&cpu14>; }; > + core3 { cpu = <&cpu15>; }; > + }; > + }; > + > + /* CLUSTER 0 */ > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x0>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x1>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x2>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x3>; > + next-level-cache = <&l2_0>; > + enable-method = "psci"; > + }; > + > + l2_0: l2-cache0 { > + compatible = "cache"; > + }; > + > + /* CLUSTER 1 */ > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x100>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x101>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x102>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0 0x103>; > + next-level-cache = <&l2_1>; > + enable-method = "psci"; > + }; > + > + l2_1: l2-cache1 { > + compatible = "cache"; This is missing properties. If you don't see warnings, update dtschema. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-04-11 13:55 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-10 18:45 [PATCH v13 00/15] Support AMD Pensando Elba SoC Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 01/15] dt-bindings: arm: add AMD Pensando boards Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-17 14:54 ` Ulf Hansson 2023-04-17 14:54 ` Ulf Hansson 2023-04-10 18:45 ` [PATCH v13 03/15] dt-bindings: spi: cdns: Add compatible for " Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-17 17:15 ` Mark Brown 2023-04-17 17:15 ` Mark Brown 2023-04-18 21:49 ` [PATCH v14 " Brad Larson 2023-04-18 21:49 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 05/15] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 06/15] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 07/15] arm64: Add config for AMD Pensando SoC platforms Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 08/15] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-11 13:55 ` Rob Herring [this message] 2023-04-11 13:55 ` Rob Herring 2023-04-13 0:51 ` Brad Larson 2023-04-13 0:51 ` Brad Larson 2023-04-21 21:05 ` [PATCH v14 " Brad Larson 2023-04-21 21:05 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 10/15] spi: dw: Add support " Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-10 18:45 ` [PATCH v13 11/15] mmc: sdhci-cadence: Enable device specific override of writel() Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-17 14:54 ` Ulf Hansson 2023-04-17 14:54 ` Ulf Hansson 2023-04-10 18:45 ` [PATCH v13 12/15] mmc: sdhci-cadence: Support device specific init during probe Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-17 14:54 ` Ulf Hansson 2023-04-17 14:54 ` Ulf Hansson 2023-04-10 18:45 ` [PATCH v13 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-17 14:54 ` Ulf Hansson 2023-04-17 14:54 ` Ulf Hansson 2023-04-10 18:45 ` [PATCH v13 14/15] mmc: sdhci-cadence: Support mmc hardware reset Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-17 14:54 ` Ulf Hansson 2023-04-17 14:54 ` Ulf Hansson 2023-04-10 18:45 ` [PATCH v13 15/15] soc: amd: Add support for AMD Pensando SoC Controller Brad Larson 2023-04-10 18:45 ` Brad Larson 2023-04-11 9:20 ` Andy Shevchenko 2023-04-11 9:20 ` Andy Shevchenko 2023-04-20 22:52 ` Brad Larson 2023-04-20 22:52 ` Brad Larson 2023-04-21 21:38 ` [PATCH v14 " Brad Larson 2023-04-21 21:38 ` Brad Larson 2023-04-17 19:28 ` (subset) [PATCH v13 00/15] Support AMD Pensando Elba SoC Mark Brown 2023-04-17 19:28 ` Mark Brown
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