From: Sunil V L <sunilvl@ventanamicro.com> To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, "Rafael J . Wysocki" <rafael@kernel.org>, Len Brown <lenb@kernel.org>, Sunil V L <sunilvl@ventanamicro.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Weili Qian <qianweili@huawei.com>, Zhou Wang <wangzhou1@hisilicon.com>, Herbert Xu <herbert@gondor.apana.org.au>, "David S . Miller" <davem@davemloft.net>, Marc Zyngier <maz@kernel.org>, Maximilian Luz <luzmaximilian@gmail.com>, Hans de Goede <hdegoede@redhat.com>, Mark Gross <markgross@kernel.org>, Nathan Chancellor <nathan@kernel.org>, Nick Desaulniers <ndesaulniers@google.com>, Tom Rix <trix@redhat.com> Subject: [PATCH V6 00/21] Add basic ACPI support for RISC-V Date: Mon, 15 May 2023 11:19:07 +0530 [thread overview] Message-ID: <20230515054928.2079268-1-sunilvl@ventanamicro.com> (raw) This patch series enables the basic ACPI infrastructure for RISC-V. Supporting external interrupt controllers is in progress and hence it is tested using poll based HVC SBI console and RAM disk. The first patch in this series is one of the patch from Jisheng's series [1] which is not merged yet. This patch is required to support ACPI since efi_init() which gets called before sbi_init() can enable static branches and hits a panic. Below are two ECRs approved by ASWG. RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view Changes since V5: 1) Reordered commits in the series to avoid intermediate build failure reported by Conor. 2) Updated hisilicon driver patch as per feedback from Herbert Xu. 3) Rebased to 6.4-rc2 Changes since V4: 1) Rebased with 6.4-rc1 which has ACPICA patches now. 2) Split cpufeature.c patch into two by adding patch 2/7 from Conor's series [2] 3) Updated caching RINTC logic to avoid global. 4) Added driver patches to enable allmodconfig build at the start of the series. 5) Updated tags Changes since V3: 1) Added two more driver patches to workaround allmodconfig build failure. 2) Separated removal of riscv_of_processor_hartid() to a different patch. 3) Addressed Conor's feedback. 4) Rebased to v6.3-rc5 and added latest tags Changes since V2: 1) Dropped ACPI_PROCESSOR patch. 2) Added new patch to print debug info of RISC-V INTC in MADT 3) Addressed other comments from Drew. 4) Rebased and updated tags Changes since V1: 1) Dropped PCI changes and instead added dummy interfaces just to enable building ACPI core when CONFIG_PCI is enabled. Actual PCI changes will be added in future along with external interrupt controller support in ACPI. 2) Squashed couple of patches so that new code added gets built in each commit. 3) Fixed the missing wake_cpu code in timer refactor patch as pointed by Conor 4) Fixed an issue with SMP disabled. 5) Addressed other comments from Conor. 6) Updated documentation patch as per feedback from Sanjaya. 7) Fixed W=1 and checkpatch --strict issues. 8) Added ACK/RB tags [1] https://lore.kernel.org/all/20220821140918.3613-1-jszhang@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/ These changes are available at https://github.com/vlsunil/linux/commits/acpi_b1_us_review_v6 Testing: 1) Build latest Qemu 2) Build EDK2 as per instructions in https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support 3) Build Linux after enabling SBI HVC and SBI earlycon CONFIG_RISCV_SBI_V01=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y 4) Build buildroot. Run with below command. qemu-system-riscv64 -nographic \ -drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \ -machine virt -smp 16 -m 2G \ -kernel arch/riscv/boot/Image \ -initrd buildroot/output/images/rootfs.cpio \ -append "root=/dev/ram ro console=hvc0 earlycon=sbi" Jisheng Zhang (1): riscv: move sbi_init() earlier before jump_label_init() Sunil V L (20): platform/surface: Disable for RISC-V crypto: hisilicon/qm: Fix to enable build with RISC-V clang ACPI: tables: Print RINTC information when MADT is parsed ACPI: OSL: Make should_use_kmap() 0 for RISC-V RISC-V: Add support to build the ACPI core ACPI: processor_core: RISC-V: Enable mapping processor to the hartid RISC-V: Add ACPI initialization in setup_arch() RISC-V: ACPI: Cache and retrieve the RINTC structure drivers/acpi: RISC-V: Add RHCT related code RISC-V: smpboot: Create wrapper setup_smp() RISC-V: smpboot: Add ACPI support in setup_smp() RISC-V: only iterate over possible CPUs in ISA string parser RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() RISC-V: cpu: Enable cpuinfo for ACPI systems irqchip/riscv-intc: Add ACPI support clocksource/timer-riscv: Refactor riscv_timer_init_dt() clocksource/timer-riscv: Add ACPI support RISC-V: time.c: Add ACPI support for time_init() RISC-V: Enable ACPI in defconfig MAINTAINERS: Add entry for drivers/acpi/riscv .../admin-guide/kernel-parameters.txt | 8 +- MAINTAINERS | 7 + arch/riscv/Kconfig | 5 + arch/riscv/configs/defconfig | 1 + arch/riscv/include/asm/acenv.h | 11 + arch/riscv/include/asm/acpi.h | 84 ++++++ arch/riscv/include/asm/cpu.h | 8 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/acpi.c | 251 ++++++++++++++++++ arch/riscv/kernel/cpu.c | 30 ++- arch/riscv/kernel/cpufeature.c | 42 ++- arch/riscv/kernel/setup.c | 11 +- arch/riscv/kernel/smpboot.c | 77 +++++- arch/riscv/kernel/time.c | 25 +- drivers/acpi/Makefile | 2 + drivers/acpi/osl.c | 2 +- drivers/acpi/processor_core.c | 29 ++ drivers/acpi/riscv/Makefile | 2 + drivers/acpi/riscv/rhct.c | 83 ++++++ drivers/acpi/tables.c | 10 + drivers/clocksource/timer-riscv.c | 92 ++++--- drivers/crypto/hisilicon/qm.c | 5 + drivers/irqchip/irq-riscv-intc.c | 70 +++-- drivers/platform/surface/aggregator/Kconfig | 2 +- 24 files changed, 772 insertions(+), 86 deletions(-) create mode 100644 arch/riscv/include/asm/acenv.h create mode 100644 arch/riscv/include/asm/acpi.h create mode 100644 arch/riscv/include/asm/cpu.h create mode 100644 arch/riscv/kernel/acpi.c create mode 100644 drivers/acpi/riscv/Makefile create mode 100644 drivers/acpi/riscv/rhct.c -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com> To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Weili Qian <qianweili@huawei.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Tom Rix <trix@redhat.com>, "Rafael J . Wysocki" <rafael@kernel.org>, Marc Zyngier <maz@kernel.org>, Jonathan Corbet <corbet@lwn.net>, Nick Desaulniers <ndesaulniers@google.com>, Mark Gross <markgross@kernel.org>, Hans de Goede <hdegoede@redhat.com>, Zhou Wang <wangzhou1@hisilicon.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Herbert Xu <herbert@gondor.apana.org.au>, Thomas Gleixner <tglx@linutronix.de>, Maximilian Luz <luzmaximilian@gmail.com>, "David S . Miller" <davem@davemloft.net>, Nathan Chancellor <nathan@kernel.org>, Len Brown <lenb@kernel.org> Subject: [PATCH V6 00/21] Add basic ACPI support for RISC-V Date: Mon, 15 May 2023 11:19:07 +0530 [thread overview] Message-ID: <20230515054928.2079268-1-sunilvl@ventanamicro.com> (raw) This patch series enables the basic ACPI infrastructure for RISC-V. Supporting external interrupt controllers is in progress and hence it is tested using poll based HVC SBI console and RAM disk. The first patch in this series is one of the patch from Jisheng's series [1] which is not merged yet. This patch is required to support ACPI since efi_init() which gets called before sbi_init() can enable static branches and hits a panic. Below are two ECRs approved by ASWG. RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view Changes since V5: 1) Reordered commits in the series to avoid intermediate build failure reported by Conor. 2) Updated hisilicon driver patch as per feedback from Herbert Xu. 3) Rebased to 6.4-rc2 Changes since V4: 1) Rebased with 6.4-rc1 which has ACPICA patches now. 2) Split cpufeature.c patch into two by adding patch 2/7 from Conor's series [2] 3) Updated caching RINTC logic to avoid global. 4) Added driver patches to enable allmodconfig build at the start of the series. 5) Updated tags Changes since V3: 1) Added two more driver patches to workaround allmodconfig build failure. 2) Separated removal of riscv_of_processor_hartid() to a different patch. 3) Addressed Conor's feedback. 4) Rebased to v6.3-rc5 and added latest tags Changes since V2: 1) Dropped ACPI_PROCESSOR patch. 2) Added new patch to print debug info of RISC-V INTC in MADT 3) Addressed other comments from Drew. 4) Rebased and updated tags Changes since V1: 1) Dropped PCI changes and instead added dummy interfaces just to enable building ACPI core when CONFIG_PCI is enabled. Actual PCI changes will be added in future along with external interrupt controller support in ACPI. 2) Squashed couple of patches so that new code added gets built in each commit. 3) Fixed the missing wake_cpu code in timer refactor patch as pointed by Conor 4) Fixed an issue with SMP disabled. 5) Addressed other comments from Conor. 6) Updated documentation patch as per feedback from Sanjaya. 7) Fixed W=1 and checkpatch --strict issues. 8) Added ACK/RB tags [1] https://lore.kernel.org/all/20220821140918.3613-1-jszhang@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20230504-divisive-unsavory-5a2ff0c3c2d1@spud/ These changes are available at https://github.com/vlsunil/linux/commits/acpi_b1_us_review_v6 Testing: 1) Build latest Qemu 2) Build EDK2 as per instructions in https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support 3) Build Linux after enabling SBI HVC and SBI earlycon CONFIG_RISCV_SBI_V01=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y 4) Build buildroot. Run with below command. qemu-system-riscv64 -nographic \ -drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \ -machine virt -smp 16 -m 2G \ -kernel arch/riscv/boot/Image \ -initrd buildroot/output/images/rootfs.cpio \ -append "root=/dev/ram ro console=hvc0 earlycon=sbi" Jisheng Zhang (1): riscv: move sbi_init() earlier before jump_label_init() Sunil V L (20): platform/surface: Disable for RISC-V crypto: hisilicon/qm: Fix to enable build with RISC-V clang ACPI: tables: Print RINTC information when MADT is parsed ACPI: OSL: Make should_use_kmap() 0 for RISC-V RISC-V: Add support to build the ACPI core ACPI: processor_core: RISC-V: Enable mapping processor to the hartid RISC-V: Add ACPI initialization in setup_arch() RISC-V: ACPI: Cache and retrieve the RINTC structure drivers/acpi: RISC-V: Add RHCT related code RISC-V: smpboot: Create wrapper setup_smp() RISC-V: smpboot: Add ACPI support in setup_smp() RISC-V: only iterate over possible CPUs in ISA string parser RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() RISC-V: cpu: Enable cpuinfo for ACPI systems irqchip/riscv-intc: Add ACPI support clocksource/timer-riscv: Refactor riscv_timer_init_dt() clocksource/timer-riscv: Add ACPI support RISC-V: time.c: Add ACPI support for time_init() RISC-V: Enable ACPI in defconfig MAINTAINERS: Add entry for drivers/acpi/riscv .../admin-guide/kernel-parameters.txt | 8 +- MAINTAINERS | 7 + arch/riscv/Kconfig | 5 + arch/riscv/configs/defconfig | 1 + arch/riscv/include/asm/acenv.h | 11 + arch/riscv/include/asm/acpi.h | 84 ++++++ arch/riscv/include/asm/cpu.h | 8 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/acpi.c | 251 ++++++++++++++++++ arch/riscv/kernel/cpu.c | 30 ++- arch/riscv/kernel/cpufeature.c | 42 ++- arch/riscv/kernel/setup.c | 11 +- arch/riscv/kernel/smpboot.c | 77 +++++- arch/riscv/kernel/time.c | 25 +- drivers/acpi/Makefile | 2 + drivers/acpi/osl.c | 2 +- drivers/acpi/processor_core.c | 29 ++ drivers/acpi/riscv/Makefile | 2 + drivers/acpi/riscv/rhct.c | 83 ++++++ drivers/acpi/tables.c | 10 + drivers/clocksource/timer-riscv.c | 92 ++++--- drivers/crypto/hisilicon/qm.c | 5 + drivers/irqchip/irq-riscv-intc.c | 70 +++-- drivers/platform/surface/aggregator/Kconfig | 2 +- 24 files changed, 772 insertions(+), 86 deletions(-) create mode 100644 arch/riscv/include/asm/acenv.h create mode 100644 arch/riscv/include/asm/acpi.h create mode 100644 arch/riscv/include/asm/cpu.h create mode 100644 arch/riscv/kernel/acpi.c create mode 100644 drivers/acpi/riscv/Makefile create mode 100644 drivers/acpi/riscv/rhct.c -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2023-05-15 5:49 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-15 5:49 Sunil V L [this message] 2023-05-15 5:49 ` [PATCH V6 00/21] Add basic ACPI support for RISC-V Sunil V L 2023-05-15 5:49 ` [PATCH V6 01/21] riscv: move sbi_init() earlier before jump_label_init() Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 02/21] platform/surface: Disable for RISC-V Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:54 ` Herbert Xu 2023-05-15 5:54 ` Herbert Xu 2023-05-15 5:49 ` [PATCH V6 04/21] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 06/21] RISC-V: Add support to build the ACPI core Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 08/21] RISC-V: Add ACPI initialization in setup_arch() Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 09/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-23 12:01 ` Andrew Jones 2023-05-23 12:01 ` Andrew Jones 2023-05-15 5:49 ` [PATCH V6 10/21] drivers/acpi: RISC-V: Add RHCT related code Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 11/21] RISC-V: smpboot: Create wrapper setup_smp() Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 12/21] RISC-V: smpboot: Add ACPI support in setup_smp() Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 13/21] RISC-V: only iterate over possible CPUs in ISA string parser Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 14/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 15/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 16/21] irqchip/riscv-intc: Add ACPI support Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 18/21] clocksource/timer-riscv: Add ACPI support Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 19/21] RISC-V: time.c: Add ACPI support for time_init() Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 20/21] RISC-V: Enable ACPI in defconfig Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-05-15 5:49 ` [PATCH V6 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L 2023-05-15 5:49 ` Sunil V L 2023-06-02 14:57 ` (subset) [PATCH V6 00/21] Add basic ACPI support for RISC-V Palmer Dabbelt 2023-06-02 14:57 ` Palmer Dabbelt 2023-06-02 15:11 ` Palmer Dabbelt 2023-06-02 15:11 ` Palmer Dabbelt 2023-06-02 15:50 ` Conor Dooley 2023-06-02 15:50 ` Conor Dooley 2023-06-02 15:54 ` Conor Dooley 2023-06-02 15:54 ` Conor Dooley 2023-06-02 15:00 ` patchwork-bot+linux-riscv 2023-06-02 15:00 ` patchwork-bot+linux-riscv
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230515054928.2079268-1-sunilvl@ventanamicro.com \ --to=sunilvl@ventanamicro.com \ --cc=aou@eecs.berkeley.edu \ --cc=corbet@lwn.net \ --cc=daniel.lezcano@linaro.org \ --cc=davem@davemloft.net \ --cc=hdegoede@redhat.com \ --cc=herbert@gondor.apana.org.au \ --cc=lenb@kernel.org \ --cc=linux-acpi@vger.kernel.org \ --cc=linux-crypto@vger.kernel.org \ --cc=linux-doc@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=llvm@lists.linux.dev \ --cc=luzmaximilian@gmail.com \ --cc=markgross@kernel.org \ --cc=maz@kernel.org \ --cc=nathan@kernel.org \ --cc=ndesaulniers@google.com \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=platform-driver-x86@vger.kernel.org \ --cc=qianweili@huawei.com \ --cc=rafael@kernel.org \ --cc=tglx@linutronix.de \ --cc=trix@redhat.com \ --cc=wangzhou1@hisilicon.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.