From: Junhao He <hejunhao3@huawei.com>
To: <will@kernel.org>, <jonathan.cameron@huawei.com>,
<linux-kernel@vger.kernel.org>, <mark.rutland@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-doc@vger.kernel.org>, <linuxarm@huawei.com>,
<yangyicong@huawei.com>, <shenyang39@huawei.com>,
<prime.zeng@hisilicon.com>, <hejunhao3@huawei.com>
Subject: [PATCH v4 3/3] docs: perf: Add new description for HiSilicon UC PMU
Date: Fri, 9 Jun 2023 15:56:08 +0800 [thread overview]
Message-ID: <20230609075608.36559-4-hejunhao3@huawei.com> (raw)
In-Reply-To: <20230609075608.36559-1-hejunhao3@huawei.com>
A new function is added on HiSilicon uncore UC PMU.
The UC PMU support to filter statistical information based on
the specified tx request uring channel. Make user configuration
through "uring_channel" parameter.
Document them to provide guidance on how to use them.
Signed-off-by: Junhao He <hejunhao3@huawei.com>
Reviewed-by: Jonathan Cameron <Jonthan.Cameron@huawei.com>
Reviewed-by: Yicong Yang <yangyicong@hisilicon.com>
---
Documentation/admin-guide/perf/hisi-pmu.rst | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst
index 546979360513..939a524fa1d6 100644
--- a/Documentation/admin-guide/perf/hisi-pmu.rst
+++ b/Documentation/admin-guide/perf/hisi-pmu.rst
@@ -98,6 +98,14 @@ CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
5'b00011: HAC_ICL;
5'b10000: PCIe_ICL;
+(e) uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
+uring channel. It is 2 bits. Some important codes are as follows:
+2'b11: count the events which sent to the uring_ext (MATA) channel;
+2'b01: is the same as 2'b11;
+2'b10: count the events which sent to the uring (non-MATA) channel;
+2'b00: default value, count the events which sent to the both uring and
+ uring_ext channel;
+
Users could configure IDs to count data come from specific CCL/ICL, by setting
srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
--
2.33.0
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WARNING: multiple messages have this Message-ID (diff)
From: Junhao He <hejunhao3@huawei.com>
To: <will@kernel.org>, <jonathan.cameron@huawei.com>,
<linux-kernel@vger.kernel.org>, <mark.rutland@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-doc@vger.kernel.org>, <linuxarm@huawei.com>,
<yangyicong@huawei.com>, <shenyang39@huawei.com>,
<prime.zeng@hisilicon.com>, <hejunhao3@huawei.com>
Subject: [PATCH v4 3/3] docs: perf: Add new description for HiSilicon UC PMU
Date: Fri, 9 Jun 2023 15:56:08 +0800 [thread overview]
Message-ID: <20230609075608.36559-4-hejunhao3@huawei.com> (raw)
In-Reply-To: <20230609075608.36559-1-hejunhao3@huawei.com>
A new function is added on HiSilicon uncore UC PMU.
The UC PMU support to filter statistical information based on
the specified tx request uring channel. Make user configuration
through "uring_channel" parameter.
Document them to provide guidance on how to use them.
Signed-off-by: Junhao He <hejunhao3@huawei.com>
Reviewed-by: Jonathan Cameron <Jonthan.Cameron@huawei.com>
Reviewed-by: Yicong Yang <yangyicong@hisilicon.com>
---
Documentation/admin-guide/perf/hisi-pmu.rst | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst
index 546979360513..939a524fa1d6 100644
--- a/Documentation/admin-guide/perf/hisi-pmu.rst
+++ b/Documentation/admin-guide/perf/hisi-pmu.rst
@@ -98,6 +98,14 @@ CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
5'b00011: HAC_ICL;
5'b10000: PCIe_ICL;
+(e) uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
+uring channel. It is 2 bits. Some important codes are as follows:
+2'b11: count the events which sent to the uring_ext (MATA) channel;
+2'b01: is the same as 2'b11;
+2'b10: count the events which sent to the uring (non-MATA) channel;
+2'b00: default value, count the events which sent to the both uring and
+ uring_ext channel;
+
Users could configure IDs to count data come from specific CCL/ICL, by setting
srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
--
2.33.0
next prev parent reply other threads:[~2023-06-09 7:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-09 7:56 [PATCH v4 0/3] Add support for HiSilicon SoC uncore PMU Junhao He
2023-06-09 7:56 ` Junhao He
2023-06-09 7:56 ` [PATCH v4 1/3] drivers/perf: hisi: Add support for HiSilicon H60PA and PAv3 PMU driver Junhao He
2023-06-09 7:56 ` Junhao He
2023-06-09 8:53 ` Mark Rutland
2023-06-09 8:53 ` Mark Rutland
2023-06-15 11:44 ` hejunhao
2023-06-15 11:44 ` hejunhao
2023-06-09 7:56 ` [PATCH v4 2/3] drivers/perf: hisi: Add support for HiSilicon UC " Junhao He
2023-06-09 7:56 ` Junhao He
2023-06-09 8:59 ` Mark Rutland
2023-06-09 8:59 ` Mark Rutland
2023-06-09 7:56 ` Junhao He [this message]
2023-06-09 7:56 ` [PATCH v4 3/3] docs: perf: Add new description for HiSilicon UC PMU Junhao He
2023-06-09 9:00 ` Mark Rutland
2023-06-09 9:00 ` Mark Rutland
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