From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Andrew Morton <akpm@linux-foundation.org>,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
"Suzuki K Poulose" <suzuki.poulose@arm.com>,
Arnd Bergmann <arnd@arndb.de>, "Oleg Nesterov" <oleg@redhat.com>,
Eric Biederman <ebiederm@xmission.com>,
"Kees Cook" <keescook@chromium.org>,
Shuah Khan <shuah@kernel.org>,
"Rick P. Edgecombe" <rick.p.edgecombe@intel.com>,
Deepak Gupta <debug@rivosinc.com>,
Ard Biesheuvel <ardb@kernel.org>,
Szabolcs Nagy <Szabolcs.Nagy@arm.com>,
"H.J. Lu" <hjl.tools@gmail.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
<linux-arm-kernel@lists.infradead.org>,
<linux-doc@vger.kernel.org>, <kvmarm@lists.linux.dev>,
<linux-fsdevel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <linux-kselftest@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 17/35] arm64/traps: Handle GCS exceptions
Date: Mon, 17 Jul 2023 13:12:30 +0100 [thread overview]
Message-ID: <20230717131230.00003569@Huawei.com> (raw)
In-Reply-To: <20230716-arm64-gcs-v1-17-bf567f93bba6@kernel.org>
On Sun, 16 Jul 2023 22:51:13 +0100
Mark Brown <broonie@kernel.org> wrote:
> A new exception code is defined for GCS specific faults other than
> standard load/store faults, for example GCS token validation failures,
> add handling for this. These faults are reported to userspace as
> segfaults with code SEGV_CPERR (protection error), mirroring the
> reporting for x86 shadow stack errors.
>
> GCS faults due to memory load/store operations generate data aborts with
> a flag set, these will be handled separately as part of the data abort
> handling.
>
> Since we do not currently enable GCS for EL1 we should not get any faults
> there but while we're at it we wire things up there, treating any GCS
> fault as fatal.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
See below.
> ---
> arch/arm64/include/asm/esr.h | 26 +++++++++++++++++++++++++-
> arch/arm64/include/asm/exception.h | 2 ++
> arch/arm64/kernel/entry-common.c | 23 +++++++++++++++++++++++
> arch/arm64/kernel/traps.c | 11 +++++++++++
> 4 files changed, 61 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index ae35939f395b..c5a72172fcf1 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
...
> @@ -382,6 +383,29 @@
> #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
> #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
>
> +/* ISS field definitions for GCS */
> +#define ESR_ELx_ExType_SHIFT (20)
> +#define ESR_ELx_ExType_MASK GENMASK(23, 20)
> +#define ESR_ELx_Raddr_SHIFT (14)
(10) ?
> +#define ESR_ELx_Raddr_MASK GENMASK(14, 10)
> +#define ESR_ELx_Rn_SHIFT (5)
> +#define ESR_ELx_Rn_MASK GENMASK(9, 5)
I think this can also be ESR_ELx_RVALUE_MASK for some ExType
Worth adding that as well?
> +#define ESR_ELx_IT_SHIFT (0)
> +#define ESR_ELx_IT_MASK GENMASK(4, 0)
> +
> +#define ESR_ELx_ExType_DATA_CHECK 0
> +#define ESR_ELx_ExType_EXLOCK 1
> +#define ESR_ELx_ExType_STR 2
> +
> +#define ESR_ELx_IT_RET 0
> +#define ESR_ELx_IT_GCSPOPM 1
> +#define ESR_ELx_IT_RET_KEYA 2
> +#define ESR_ELx_IT_RET_KEYB 3
> +#define ESR_ELx_IT_GCSSS1 4
> +#define ESR_ELx_IT_GCSSS2 5
> +#define ESR_ELx_IT_GCSPOPCX 6
> +#define ESR_ELx_IT_GCSPOPX 7
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Andrew Morton <akpm@linux-foundation.org>,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
"Suzuki K Poulose" <suzuki.poulose@arm.com>,
Arnd Bergmann <arnd@arndb.de>, "Oleg Nesterov" <oleg@redhat.com>,
Eric Biederman <ebiederm@xmission.com>,
"Kees Cook" <keescook@chromium.org>,
Shuah Khan <shuah@kernel.org>,
"Rick P. Edgecombe" <rick.p.edgecombe@intel.com>,
Deepak Gupta <debug@rivosinc.com>,
Ard Biesheuvel <ardb@kernel.org>,
Szabolcs Nagy <Szabolcs.Nagy@arm.com>,
"H.J. Lu" <hjl.tools@gmail.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
<linux-arm-kernel@lists.infradead.org>,
<linux-doc@vger.kernel.org>, <kvmarm@lists.linux.dev>,
<linux-fsdevel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <linux-kselftest@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 17/35] arm64/traps: Handle GCS exceptions
Date: Mon, 17 Jul 2023 13:12:30 +0100 [thread overview]
Message-ID: <20230717131230.00003569@Huawei.com> (raw)
In-Reply-To: <20230716-arm64-gcs-v1-17-bf567f93bba6@kernel.org>
On Sun, 16 Jul 2023 22:51:13 +0100
Mark Brown <broonie@kernel.org> wrote:
> A new exception code is defined for GCS specific faults other than
> standard load/store faults, for example GCS token validation failures,
> add handling for this. These faults are reported to userspace as
> segfaults with code SEGV_CPERR (protection error), mirroring the
> reporting for x86 shadow stack errors.
>
> GCS faults due to memory load/store operations generate data aborts with
> a flag set, these will be handled separately as part of the data abort
> handling.
>
> Since we do not currently enable GCS for EL1 we should not get any faults
> there but while we're at it we wire things up there, treating any GCS
> fault as fatal.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
See below.
> ---
> arch/arm64/include/asm/esr.h | 26 +++++++++++++++++++++++++-
> arch/arm64/include/asm/exception.h | 2 ++
> arch/arm64/kernel/entry-common.c | 23 +++++++++++++++++++++++
> arch/arm64/kernel/traps.c | 11 +++++++++++
> 4 files changed, 61 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index ae35939f395b..c5a72172fcf1 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
...
> @@ -382,6 +383,29 @@
> #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
> #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
>
> +/* ISS field definitions for GCS */
> +#define ESR_ELx_ExType_SHIFT (20)
> +#define ESR_ELx_ExType_MASK GENMASK(23, 20)
> +#define ESR_ELx_Raddr_SHIFT (14)
(10) ?
> +#define ESR_ELx_Raddr_MASK GENMASK(14, 10)
> +#define ESR_ELx_Rn_SHIFT (5)
> +#define ESR_ELx_Rn_MASK GENMASK(9, 5)
I think this can also be ESR_ELx_RVALUE_MASK for some ExType
Worth adding that as well?
> +#define ESR_ELx_IT_SHIFT (0)
> +#define ESR_ELx_IT_MASK GENMASK(4, 0)
> +
> +#define ESR_ELx_ExType_DATA_CHECK 0
> +#define ESR_ELx_ExType_EXLOCK 1
> +#define ESR_ELx_ExType_STR 2
> +
> +#define ESR_ELx_IT_RET 0
> +#define ESR_ELx_IT_GCSPOPM 1
> +#define ESR_ELx_IT_RET_KEYA 2
> +#define ESR_ELx_IT_RET_KEYB 3
> +#define ESR_ELx_IT_GCSSS1 4
> +#define ESR_ELx_IT_GCSSS2 5
> +#define ESR_ELx_IT_GCSPOPCX 6
> +#define ESR_ELx_IT_GCSPOPX 7
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Andrew Morton <akpm@linux-foundation.org>,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Arnd Bergmann <arnd@arndb.de>, Oleg Nesterov <oleg@redhat.com>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <keescook@chromium.org>, Shuah Khan <shuah@kernel.org>,
"Rick P. Edgecombe" <rick.p.edgecombe@intel.com>,
Deepak Gupta <debug@rivosinc.com>,
Ard Biesheuvel <ardb@kernel.org>,
Szabolcs Nagy <Szabolcs.Nagy@arm.com>,
"H.J. Lu" <hjl.tools@gmail.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 17/35] arm64/traps: Handle GCS exceptions
Date: Mon, 17 Jul 2023 13:12:30 +0100 [thread overview]
Message-ID: <20230717131230.00003569@Huawei.com> (raw)
In-Reply-To: <20230716-arm64-gcs-v1-17-bf567f93bba6@kernel.org>
On Sun, 16 Jul 2023 22:51:13 +0100
Mark Brown <broonie@kernel.org> wrote:
> A new exception code is defined for GCS specific faults other than
> standard load/store faults, for example GCS token validation failures,
> add handling for this. These faults are reported to userspace as
> segfaults with code SEGV_CPERR (protection error), mirroring the
> reporting for x86 shadow stack errors.
>
> GCS faults due to memory load/store operations generate data aborts with
> a flag set, these will be handled separately as part of the data abort
> handling.
>
> Since we do not currently enable GCS for EL1 we should not get any faults
> there but while we're at it we wire things up there, treating any GCS
> fault as fatal.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
See below.
> ---
> arch/arm64/include/asm/esr.h | 26 +++++++++++++++++++++++++-
> arch/arm64/include/asm/exception.h | 2 ++
> arch/arm64/kernel/entry-common.c | 23 +++++++++++++++++++++++
> arch/arm64/kernel/traps.c | 11 +++++++++++
> 4 files changed, 61 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index ae35939f395b..c5a72172fcf1 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
...
> @@ -382,6 +383,29 @@
> #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
> #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
>
> +/* ISS field definitions for GCS */
> +#define ESR_ELx_ExType_SHIFT (20)
> +#define ESR_ELx_ExType_MASK GENMASK(23, 20)
> +#define ESR_ELx_Raddr_SHIFT (14)
(10) ?
> +#define ESR_ELx_Raddr_MASK GENMASK(14, 10)
> +#define ESR_ELx_Rn_SHIFT (5)
> +#define ESR_ELx_Rn_MASK GENMASK(9, 5)
I think this can also be ESR_ELx_RVALUE_MASK for some ExType
Worth adding that as well?
> +#define ESR_ELx_IT_SHIFT (0)
> +#define ESR_ELx_IT_MASK GENMASK(4, 0)
> +
> +#define ESR_ELx_ExType_DATA_CHECK 0
> +#define ESR_ELx_ExType_EXLOCK 1
> +#define ESR_ELx_ExType_STR 2
> +
> +#define ESR_ELx_IT_RET 0
> +#define ESR_ELx_IT_GCSPOPM 1
> +#define ESR_ELx_IT_RET_KEYA 2
> +#define ESR_ELx_IT_RET_KEYB 3
> +#define ESR_ELx_IT_GCSSS1 4
> +#define ESR_ELx_IT_GCSSS2 5
> +#define ESR_ELx_IT_GCSPOPCX 6
> +#define ESR_ELx_IT_GCSPOPX 7
_______________________________________________
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next prev parent reply other threads:[~2023-07-17 12:12 UTC|newest]
Thread overview: 153+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-16 21:50 [PATCH 00/35] arm64/gcs: Provide support for GCS at EL0 Mark Brown
2023-07-16 21:50 ` Mark Brown
2023-07-16 21:50 ` Mark Brown
2023-07-16 21:50 ` [PATCH 01/35] prctl: arch-agnostic prctl for shadow stack Mark Brown
2023-07-16 21:50 ` Mark Brown
2023-07-16 21:50 ` Mark Brown
2023-07-18 17:45 ` Edgecombe, Rick P
2023-07-18 17:45 ` Edgecombe, Rick P
2023-07-18 17:45 ` Edgecombe, Rick P
2023-07-18 18:54 ` Mark Brown
2023-07-18 18:54 ` Mark Brown
2023-07-18 18:54 ` Mark Brown
2023-07-16 21:50 ` [PATCH 02/35] prctl: Add flag for shadow stack writeability and push/pop Mark Brown
2023-07-16 21:50 ` Mark Brown
2023-07-16 21:50 ` Mark Brown
2023-07-18 17:47 ` Edgecombe, Rick P
2023-07-18 17:47 ` Edgecombe, Rick P
2023-07-18 17:47 ` Edgecombe, Rick P
2023-07-18 19:10 ` Mark Brown
2023-07-18 19:10 ` Mark Brown
2023-07-18 19:10 ` Mark Brown
2023-07-16 21:50 ` [PATCH 03/35] arm64: Document boot requirements for Guarded Control Stacks Mark Brown
2023-07-16 21:50 ` Mark Brown
2023-07-16 21:50 ` Mark Brown
2023-07-16 21:51 ` [PATCH 04/35] arm64/gcs: Document the ABI " Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-17 11:42 ` Jonathan Cameron
2023-07-17 11:42 ` Jonathan Cameron
2023-07-17 11:42 ` Jonathan Cameron
2023-07-19 11:44 ` Mike Rapoport
2023-07-19 11:44 ` Mike Rapoport
2023-07-19 11:44 ` Mike Rapoport
2023-07-19 13:25 ` Mark Brown
2023-07-19 13:25 ` Mark Brown
2023-07-19 13:25 ` Mark Brown
2023-07-19 14:04 ` Mike Rapoport
2023-07-19 14:04 ` Mike Rapoport
2023-07-19 14:04 ` Mike Rapoport
2023-07-16 21:51 ` [PATCH 05/35] arm64/sysreg: Add new system registers for GCS Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 06/35] arm64/sysreg: Add definitions for architected GCS caps Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 07/35] arm64/gcs: Add manual encodings of GCS instructions Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 08/35] arm64/gcs: Provide copy_to_user_gcs() Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 09/35] arm64/cpufeature: Runtime detection of Guarded Control Stack (GCS) Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 10/35] arm64/mm: Allocate PIE slots for EL0 guarded control stack Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 11/35] mm: Define VM_SHADOW_STACK for arm64 when we support GCS Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 12/35] arm64/mm: Map pages for guarded control stack Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 13/35] KVM: arm64: Manage GCS registers for guests Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 14/35] arm64: Disable traps for GCS usage at EL0 and EL1 Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 15/35] arm64/idreg: Add overrride for GCS Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 16/35] arm64/hwcap: Add hwcap " Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 17/35] arm64/traps: Handle GCS exceptions Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-17 12:12 ` Jonathan Cameron [this message]
2023-07-17 12:12 ` Jonathan Cameron
2023-07-17 12:12 ` Jonathan Cameron
2023-07-16 21:51 ` [PATCH 18/35] arm64/mm: Handle GCS data aborts Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 19/35] arm64/gcs: Context switch GCS registers for EL0 Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 20/35] arm64/gcs: Allocate a new GCS for threads with GCS enabled Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 21/35] arm64/gcs: Implement shadow stack prctl() interface Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-18 17:51 ` Edgecombe, Rick P
2023-07-18 17:51 ` Edgecombe, Rick P
2023-07-18 17:51 ` Edgecombe, Rick P
2023-07-18 19:37 ` Mark Brown
2023-07-18 19:37 ` Mark Brown
2023-07-18 19:37 ` Mark Brown
2023-07-16 21:51 ` [PATCH 22/35] arm64/mm: Implement map_shadow_stack() Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-18 9:10 ` Szabolcs Nagy
2023-07-18 9:10 ` Szabolcs Nagy
2023-07-18 9:10 ` Szabolcs Nagy
2023-07-18 13:55 ` Mark Brown
2023-07-18 13:55 ` Mark Brown
2023-07-18 13:55 ` Mark Brown
2023-07-18 15:49 ` Edgecombe, Rick P
2023-07-18 15:49 ` Edgecombe, Rick P
2023-07-18 15:49 ` Edgecombe, Rick P
2023-07-16 21:51 ` [PATCH 23/35] arm64/signal: Set up and restore the GCS context for signal handlers Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 24/35] arm64/signal: Expose GCS state in signal frames Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 25/35] arm64/ptrace: Expose GCS via ptrace and core files Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 26/35] arm64: Add Kconfig for Guarded Control Stack (GCS) Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-17 12:32 ` Jonathan Cameron
2023-07-17 12:32 ` Jonathan Cameron
2023-07-17 12:32 ` Jonathan Cameron
2023-07-16 21:51 ` [PATCH 27/35] kselftest/arm64: Verify the GCS hwcap Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 28/35] kselftest/arm64: Add GCS as a detected feature in the signal tests Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 29/35] kselftest/arm64: Add framework support for GCS to signal handling tests Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 30/35] kselftest/arm64: Allow signals tests to specify an expected si_code Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 31/35] kselftest/arm64: Always run signals tests with GCS enabled Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 32/35] kselftest/arm64: Add very basic GCS test program Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 33/35] kselftest/arm64: Add a GCS test program built with the system libc Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 34/35] selftests/arm64: Add GCS signal tests Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` [PATCH 35/35] kselftest/arm64: Enable GCS for the FP stress tests Mark Brown
2023-07-16 21:51 ` Mark Brown
2023-07-16 21:51 ` Mark Brown
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