From: Biju Das <biju.das.jz@bp.renesas.com> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> Cc: Biju Das <biju.das.jz@bp.renesas.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH v2 1/3] arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash Date: Thu, 31 Aug 2023 07:36:33 +0100 [thread overview] Message-ID: <20230831063635.2816-2-biju.das.jz@bp.renesas.com> (raw) In-Reply-To: <20230831063635.2816-1-biju.das.jz@bp.renesas.com> Enable Renesas at25ql128a flash connected to QSPI0. Also disable the node from rzfive-smarc-som as it is untested. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v1->v2: * Enabled 4-bit tx support --- .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 44 +++++++++++++++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 4 ++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 97cdad2a12e2..b9e4e476ff7b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -179,6 +179,18 @@ eth1_pins: eth1 { <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */ }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL"; + power-source = <1800>; + }; + }; + sdhi0_emmc_pins: sd0emmc { sd0_emmc_data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", @@ -230,6 +242,38 @@ sd0_mux_uhs { }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x200000>; + read-only; + }; + user@200000 { + reg = <0x200000 0xE00000>; + }; + }; + }; +}; + #if (SW_SW0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_emmc_pins>; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi index c62debc7ca7e..0c9d72c32879 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -42,6 +42,10 @@ phy1: ethernet-phy@7 { }; }; +&sbc { + status = "disabled"; +}; + &sdhi0 { status = "disabled"; }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Biju Das <biju.das.jz@bp.renesas.com> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> Cc: Biju Das <biju.das.jz@bp.renesas.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH v2 1/3] arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash Date: Thu, 31 Aug 2023 07:36:33 +0100 [thread overview] Message-ID: <20230831063635.2816-2-biju.das.jz@bp.renesas.com> (raw) In-Reply-To: <20230831063635.2816-1-biju.das.jz@bp.renesas.com> Enable Renesas at25ql128a flash connected to QSPI0. Also disable the node from rzfive-smarc-som as it is untested. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v1->v2: * Enabled 4-bit tx support --- .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 44 +++++++++++++++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 4 ++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 97cdad2a12e2..b9e4e476ff7b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -179,6 +179,18 @@ eth1_pins: eth1 { <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */ }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL"; + power-source = <1800>; + }; + }; + sdhi0_emmc_pins: sd0emmc { sd0_emmc_data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", @@ -230,6 +242,38 @@ sd0_mux_uhs { }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x200000>; + read-only; + }; + user@200000 { + reg = <0x200000 0xE00000>; + }; + }; + }; +}; + #if (SW_SW0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_emmc_pins>; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi index c62debc7ca7e..0c9d72c32879 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -42,6 +42,10 @@ phy1: ethernet-phy@7 { }; }; +&sbc { + status = "disabled"; +}; + &sdhi0 { status = "disabled"; }; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-08-31 6:36 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-08-31 6:36 [PATCH v2 0/3] Enable 4-bit tx support Biju Das 2023-08-31 6:36 ` Biju Das 2023-08-31 6:36 ` Biju Das [this message] 2023-08-31 6:36 ` [PATCH v2 1/3] arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash Biju Das 2023-08-31 17:31 ` Geert Uytterhoeven 2023-08-31 17:31 ` Geert Uytterhoeven 2023-09-01 7:05 ` Biju Das 2023-09-01 7:05 ` Biju Das 2023-08-31 6:36 ` [PATCH v2 2/3] arm64: dts: renesas: rzg2l-smarc-som: Enable 4-bit tx support Biju Das 2023-08-31 17:32 ` Geert Uytterhoeven 2023-08-31 6:36 ` [PATCH v2 3/3] arm64: dts: renesas: rzg2lc-smarc-som: " Biju Das 2023-08-31 17:32 ` Geert Uytterhoeven
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