From: Rob Herring <robh@kernel.org> To: Gatien Chevallier <gatien.chevallier@foss.st.com> Cc: Oleksii_Moisieiev@epam.com, gregkh@linuxfoundation.org, herbert@gondor.apana.org.au, davem@davemloft.net, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alexandre.torgue@foss.st.com, vkoul@kernel.org, jic23@kernel.org, olivier.moysan@foss.st.com, arnaud.pouliquen@foss.st.com, mchehab@kernel.org, fabrice.gasnier@foss.st.com, andi.shyti@kernel.org, ulf.hansson@linaro.org, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, hugues.fruchet@foss.st.com, lee@kernel.org, will@kernel.org, catalin.marinas@arm.com, arnd@kernel.org, richardcochran@gmail.com, Frank Rowand <frowand.list@gmail.com>, peng.fan@oss.nxp.com, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-iio@vger.kernel.org, alsa-devel@alsa-project.org, linux-media@vger.kernel.org, linux-mmc@vger.kernel.org, netdev@vger.kernel.org, linux-p hy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org Subject: Re: [PATCH v5 03/11] dt-bindings: bus: document RIFSC Date: Mon, 2 Oct 2023 13:30:41 -0500 [thread overview] Message-ID: <20231002183041.GA2062984-robh@kernel.org> (raw) In-Reply-To: <20230929142852.578394-4-gatien.chevallier@foss.st.com> On Fri, Sep 29, 2023 at 04:28:44PM +0200, Gatien Chevallier wrote: > Document RIFSC (RIF security controller). RIFSC is a firewall controller > composed of different kinds of hardware resources. > > Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> > --- > > Changes in V5: > - Renamed feature-domain* to access-control* > > Changes in V2: > - Corrected errors highlighted by Rob's robot > - No longer define the maxItems for the "feature-domains" > property > - Fix example (node name, status) > - Declare "feature-domain-names" as an optional > property for child nodes > - Fix description of "feature-domains" property > > .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > > diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > new file mode 100644 > index 000000000000..c28fceff3036 > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: STM32 Resource isolation framework security controller > + > +maintainers: > + - Gatien Chevallier <gatien.chevallier@foss.st.com> > + > +description: | > + Resource isolation framework (RIF) is a comprehensive set of hardware blocks > + designed to enforce and manage isolation of STM32 hardware resources like > + memory and peripherals. > + > + The RIFSC (RIF security controller) is composed of three sets of registers, > + each managing a specific set of hardware resources: > + - RISC registers associated with RISUP logic (resource isolation device unit > + for peripherals), assign all non-RIF aware peripherals to zero, one or > + any security domains (secure, privilege, compartment). > + - RIMC registers: associated with RIMU logic (resource isolation master > + unit), assign all non RIF-aware bus master to one security domain by > + setting secure, privileged and compartment information on the system bus. > + Alternatively, the RISUP logic controlling the device port access to a > + peripheral can assign target bus attributes to this peripheral master port > + (supported attribute: CID). > + - RISC registers associated with RISAL logic (resource isolation device unit > + for address space - Lite version), assign address space subregions to one > + security domains (secure, privilege, compartment). > + > +properties: > + compatible: > + contains: > + const: st,stm32mp25-rifsc > + > + reg: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 > + > + ranges: true > + > + "#access-controller-cells": > + const: 1 You should define what the cells contain here. > + > + access-control-provider: true > + > +patternProperties: > + "^.*@[0-9a-f]+$": > + description: Peripherals > + type: object additionalProperties: true > + properties: > + access-controller: > + minItems: 1 > + description: > + The phandle of the firewall controller of the peripheral and the > + platform-specific firewall ID of the peripheral. > + > + access-controller-names: > + minItems: 1 Drop all this. You have to define these in the specific device schemas anyways. > + > + required: > + - access-controller > + > +required: > + - compatible > + - reg > + - "#address-cells" > + - "#size-cells" > + - access-control-provider > + - "#access-controller-cells" > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + // In this example, the usart2 device refers to rifsc as its domain > + // controller. > + // Access rights are verified before creating devices. > + > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + rifsc: bus@42080000 { > + compatible = "st,stm32mp25-rifsc"; > + reg = <0x42080000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + access-control-provider; > + #access-controller-cells = <1>; > + ranges; > + > + usart2: serial@400e0000 { > + compatible = "st,stm32h7-uart"; > + reg = <0x400e0000 0x400>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ck_flexgen_08>; > + access-controller = <&rifsc 32>; > + }; > + }; > -- > 2.25.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org> To: Gatien Chevallier <gatien.chevallier@foss.st.com> Cc: Oleksii_Moisieiev@epam.com, gregkh@linuxfoundation.org, herbert@gondor.apana.org.au, davem@davemloft.net, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alexandre.torgue@foss.st.com, vkoul@kernel.org, jic23@kernel.org, olivier.moysan@foss.st.com, arnaud.pouliquen@foss.st.com, mchehab@kernel.org, fabrice.gasnier@foss.st.com, andi.shyti@kernel.org, ulf.hansson@linaro.org, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, hugues.fruchet@foss.st.com, lee@kernel.org, will@kernel.org, catalin.marinas@arm.com, arnd@kernel.org, richardcochran@gmail.com, Frank Rowand <frowand.list@gmail.com>, peng.fan@oss.nxp.com, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-iio@vger.kernel.org, alsa-devel@alsa-project.org, linux-media@vger.kernel.org, linux-mmc@vger.kernel.org, netdev@vger.kernel.org, linux-p@alsa-project.org, hy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org Subject: Re: [PATCH v5 03/11] dt-bindings: bus: document RIFSC Date: Mon, 2 Oct 2023 13:30:41 -0500 [thread overview] Message-ID: <20231002183041.GA2062984-robh@kernel.org> (raw) In-Reply-To: <20230929142852.578394-4-gatien.chevallier@foss.st.com> On Fri, Sep 29, 2023 at 04:28:44PM +0200, Gatien Chevallier wrote: > Document RIFSC (RIF security controller). RIFSC is a firewall controller > composed of different kinds of hardware resources. > > Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> > --- > > Changes in V5: > - Renamed feature-domain* to access-control* > > Changes in V2: > - Corrected errors highlighted by Rob's robot > - No longer define the maxItems for the "feature-domains" > property > - Fix example (node name, status) > - Declare "feature-domain-names" as an optional > property for child nodes > - Fix description of "feature-domains" property > > .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > > diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > new file mode 100644 > index 000000000000..c28fceff3036 > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: STM32 Resource isolation framework security controller > + > +maintainers: > + - Gatien Chevallier <gatien.chevallier@foss.st.com> > + > +description: | > + Resource isolation framework (RIF) is a comprehensive set of hardware blocks > + designed to enforce and manage isolation of STM32 hardware resources like > + memory and peripherals. > + > + The RIFSC (RIF security controller) is composed of three sets of registers, > + each managing a specific set of hardware resources: > + - RISC registers associated with RISUP logic (resource isolation device unit > + for peripherals), assign all non-RIF aware peripherals to zero, one or > + any security domains (secure, privilege, compartment). > + - RIMC registers: associated with RIMU logic (resource isolation master > + unit), assign all non RIF-aware bus master to one security domain by > + setting secure, privileged and compartment information on the system bus. > + Alternatively, the RISUP logic controlling the device port access to a > + peripheral can assign target bus attributes to this peripheral master port > + (supported attribute: CID). > + - RISC registers associated with RISAL logic (resource isolation device unit > + for address space - Lite version), assign address space subregions to one > + security domains (secure, privilege, compartment). > + > +properties: > + compatible: > + contains: > + const: st,stm32mp25-rifsc > + > + reg: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 > + > + ranges: true > + > + "#access-controller-cells": > + const: 1 You should define what the cells contain here. > + > + access-control-provider: true > + > +patternProperties: > + "^.*@[0-9a-f]+$": > + description: Peripherals > + type: object additionalProperties: true > + properties: > + access-controller: > + minItems: 1 > + description: > + The phandle of the firewall controller of the peripheral and the > + platform-specific firewall ID of the peripheral. > + > + access-controller-names: > + minItems: 1 Drop all this. You have to define these in the specific device schemas anyways. > + > + required: > + - access-controller > + > +required: > + - compatible > + - reg > + - "#address-cells" > + - "#size-cells" > + - access-control-provider > + - "#access-controller-cells" > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + // In this example, the usart2 device refers to rifsc as its domain > + // controller. > + // Access rights are verified before creating devices. > + > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + rifsc: bus@42080000 { > + compatible = "st,stm32mp25-rifsc"; > + reg = <0x42080000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + access-control-provider; > + #access-controller-cells = <1>; > + ranges; > + > + usart2: serial@400e0000 { > + compatible = "st,stm32h7-uart"; > + reg = <0x400e0000 0x400>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ck_flexgen_08>; > + access-controller = <&rifsc 32>; > + }; > + }; > -- > 2.25.1 >
next prev parent reply other threads:[~2023-10-02 18:30 UTC|newest] Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-09-29 14:28 [PATCH v5 00/11] Introduce STM32 Firewall framework Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` [PATCH v5 01/11] dt-bindings: document generic access controller Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 15:35 ` Rob Herring 2023-09-29 15:35 ` Rob Herring 2023-10-02 9:10 ` Gatien CHEVALLIER 2023-10-02 9:10 ` Gatien CHEVALLIER 2023-10-02 9:10 ` Gatien CHEVALLIER 2023-10-02 17:30 ` Rob Herring 2023-10-02 17:30 ` Rob Herring 2023-10-03 7:45 ` Gatien CHEVALLIER 2023-10-03 7:45 ` Gatien CHEVALLIER 2023-09-29 14:28 ` [PATCH v5 02/11] dt-bindings: treewide: add access-controller description Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 15:35 ` Rob Herring 2023-09-29 15:35 ` Rob Herring 2023-09-29 15:35 ` Rob Herring 2023-09-29 15:35 ` Rob Herring 2023-09-29 14:28 ` [PATCH v5 03/11] dt-bindings: bus: document RIFSC Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 15:35 ` Rob Herring 2023-09-29 15:35 ` Rob Herring 2023-10-02 18:30 ` Rob Herring [this message] 2023-10-02 18:30 ` Rob Herring 2023-10-03 7:57 ` Gatien CHEVALLIER 2023-10-03 7:57 ` Gatien CHEVALLIER 2023-09-29 14:28 ` [PATCH v5 04/11] dt-bindings: bus: document ETZPC Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 15:35 ` Rob Herring 2023-09-29 15:35 ` Rob Herring 2023-09-29 14:28 ` [PATCH v5 05/11] firewall: introduce stm32_firewall framework Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` [PATCH v5 06/11] of: property: fw_devlink: Add support for "access-controller" Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` [PATCH v5 07/11] bus: rifsc: introduce RIFSC firewall controller driver Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` [PATCH v5 08/11] arm64: dts: st: add RIFSC as an access controller for STM32MP25x boards Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` [PATCH v5 09/11] bus: etzpc: introduce ETZPC firewall controller driver Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` [PATCH v5 10/11] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` [PATCH v5 11/11] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier 2023-09-29 14:28 ` Gatien Chevallier
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