From: Jonathan Cameron via <qemu-devel@nongnu.org> To: Li Zhijian <lizhijian@fujitsu.com> Cc: <fan.ni@samsung.com>, <qemu-devel@nongnu.org>, <philmd@linaro.org>, <mst@redhat.com> Subject: Re: [PATCH v2 1/2] hw/cxl: Pass CXLComponentState to cache_mem_ops Date: Thu, 19 Oct 2023 11:50:39 +0100 [thread overview] Message-ID: <20231019115039.0000743c@Huawei.com> (raw) In-Reply-To: <20231018082408.888098-1-lizhijian@fujitsu.com> On Wed, 18 Oct 2023 16:24:07 +0800 Li Zhijian <lizhijian@fujitsu.com> wrote: > cache_mem_ops.{read,write}() interprets opaque as > CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs). > > Fortunately, cregs is the first member of cxl_cstate, so their values are > the same. > > Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)") > Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Both these lgtm. I'll carry them on my CXL tree and add them to the next series I send out for general cleaup etc, but if you send them again cc Michael Tsirkin so he has the option to pick them up directly if he wishes (all CXL changes got through Michael currently). > --- > V2: change the source side since cache_mem_ops.{read,write}() will use > cxl_cstate. > --- > hw/cxl/cxl-component-utils.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index f3bbf0fd131..6214dcdcc12 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -179,7 +179,7 @@ void cxl_component_register_block_init(Object *obj, > /* io registers controls link which we don't care about in QEMU */ > memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", > CXL2_COMPONENT_IO_REGION_SIZE); > - memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, > + memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate, > ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); > > memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com> To: Li Zhijian <lizhijian@fujitsu.com> Cc: <fan.ni@samsung.com>, <qemu-devel@nongnu.org>, <philmd@linaro.org>, <mst@redhat.com> Subject: Re: [PATCH v2 1/2] hw/cxl: Pass CXLComponentState to cache_mem_ops Date: Thu, 19 Oct 2023 11:50:39 +0100 [thread overview] Message-ID: <20231019115039.0000743c@Huawei.com> (raw) Message-ID: <20231019105039.4zF9cW1MZpONyzJXn-LlZVEySzlkf485JIcyIozqOKo@z> (raw) In-Reply-To: <20231018082408.888098-1-lizhijian@fujitsu.com> On Wed, 18 Oct 2023 16:24:07 +0800 Li Zhijian <lizhijian@fujitsu.com> wrote: > cache_mem_ops.{read,write}() interprets opaque as > CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs). > > Fortunately, cregs is the first member of cxl_cstate, so their values are > the same. > > Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)") > Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Both these lgtm. I'll carry them on my CXL tree and add them to the next series I send out for general cleaup etc, but if you send them again cc Michael Tsirkin so he has the option to pick them up directly if he wishes (all CXL changes got through Michael currently). > --- > V2: change the source side since cache_mem_ops.{read,write}() will use > cxl_cstate. > --- > hw/cxl/cxl-component-utils.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index f3bbf0fd131..6214dcdcc12 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -179,7 +179,7 @@ void cxl_component_register_block_init(Object *obj, > /* io registers controls link which we don't care about in QEMU */ > memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", > CXL2_COMPONENT_IO_REGION_SIZE); > - memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, > + memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate, > ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); > > memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
next prev parent reply other threads:[~2023-10-19 10:51 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-18 8:24 [PATCH v2 1/2] hw/cxl: Pass CXLComponentState to cache_mem_ops Li Zhijian 2023-10-18 8:24 ` [PATCH v2 2/2] hw/cxl: Pass NULL for a NULL MemoryRegionOps Li Zhijian 2023-10-19 10:50 ` Jonathan Cameron via [this message] 2023-10-19 10:50 ` [PATCH v2 1/2] hw/cxl: Pass CXLComponentState to cache_mem_ops Jonathan Cameron 2023-10-23 8:20 ` Zhijian Li (Fujitsu)
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