Re: [PATCH v3 6/6] riscv: dts: microchip: add the mpfs' system controller qspi & associated flash

From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Moritz Fischer <mdf@kernel.org>, Wu Hao <hao.wu@intel.com>,
	Xu Yilun <yilun.xu@intel.com>, Tom Rix <trix@redhat.com>,
	Russ Weight <russell.h.weight@intel.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org
Subject: Re: [PATCH v3 6/6] riscv: dts: microchip: add the mpfs' system controller qspi & associated flash
Date: Wed, 25 Oct 2023 13:22:03 +0100	[thread overview]
Message-ID: <20231025-demystify-iodize-cd93fedfd7ff@spud> (raw)
In-Reply-To: <20231020-unrated-uproar-c911c6185ae9@spud>

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On Fri, Oct 20, 2023 at 02:18:44PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The system controller's flash can be accessed via an MSS-exposed QSPI
> controller sitting, which sits between the mailbox's control & data
> registers. On Icicle, it has an MT25QL01GBBB8ESF connected to it.
> 
> The system controller and MSS both have separate QSPI controllers, both
> of which can access the flash, although the system controller takes
> priority.
> Unfortunately, on engineering sample silicon, such as that on Icicle
> kits, the MSS' QSPI controller cannot write to the flash due to a bug.
> As a workaround, a QSPI controller can be implemented in the FPGA
> fabric and the IO routing modified to connect it to the flash in place
> of the "hard" controller in the MSS.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../boot/dts/microchip/mpfs-icicle-kit.dts    | 21 +++++++++++++++++++
>  arch/riscv/boot/dts/microchip/mpfs.dtsi       | 17 +++++++++++++++
>  2 files changed, 38 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> index 90b261114763..2dae3f8f33f6 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> @@ -199,6 +199,27 @@ &syscontroller {
>  	status = "okay";
>  };
>  
> +&syscontroller_qspi {
> +	/*
> +	 * The flash *is* there, but Icicle kits that have engineering sample
> +	 * silicon (write?) access to this flash to non-functional. The system
> +	 * controller itself can actually access it, but the MSS cannot write
> +	 * an image there. Instantiating a coreQSPI in the fabric & connecting
> +	 * it to the flash instead should work though. Pre-production or later
> +	 * silicon does not have this issue.
> +	 */
> +	status = "disabled";
> +
> +	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
> +		compatible = "jedec,spi-nor";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		spi-max-frequency = <20000000>;
> +		spi-rx-bus-width = <1>;
> +		reg = <0>;
> +	};
> +};

Hmm, I think I will drop this part of the patch, and instead add the
flash for the sev-kit (which does work correctly) to avoid any confusion
as to why this is not supported on the current icicle kit boards.

Cheers,
Conor.

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