[PATCH v5 0/5] Add ISA extension smcntrpmf support

From: Atish Patra <atishp@rivosinc.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	Weiwei Li <liwei1518@gmail.com>,
	kaiwenxue1@gmail.com
Subject: [PATCH v5 0/5] Add ISA extension smcntrpmf support
Date: Wed, 28 Feb 2024 10:51:11 -0800	[thread overview]
Message-ID: <20240228185116.1321730-1-atishp@rivosinc.com> (raw)

This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. It is based on Kevin's earlier work but improves
it by actually implement privilege mode filtering by tracking the privilege
mode switches. This enables the privilege mode filtering for mhpmcounters as
well. However, Smcntrpmf/Sscofpmf must be enabled to leverage this. This series
also modified to report the raw instruction count instead of virtual cpu time
based on the instruction count when icount is enabled. The former seems to be
the preferred approach for instruction count for other architectures as well.

Please let me know if anybody thinks that's incorrect.

The series is also available at

Changes from v4->v5:
1. Rebased on top of master(158a054c4d1a).
2. Fixed a bug for VS<->HS transition.

Changes from v3->v4:
1. Fixed the ordering of the ISA extension names in isa_edata_arr.
2. Added RB tags.

Changes from v2->v3:
1. Fixed the rebasing error in PATCH2.
2. Added RB tags.
3. Addressed other review comments. 

Changes from v1->v2:
1. Implemented actual mode filtering for both icount and host ticks mode.
1. Addressed comments in v1.
2. Added Kevin's personal email address.

[1] https://github.com/riscv/riscv-smcntrpmf
[2] https://github.com/atishp04/qemu/tree/smcntrpmf_v5

Atish Patra (2):
target/riscv: Fix the predicate functions for mhpmeventhX CSRs
target/riscv: Implement privilege mode filtering for cycle/instret

Kaiwen Xue (3):
target/riscv: Add cycle & instret privilege mode filtering properties
target/riscv: Add cycle & instret privilege mode filtering definitions
target/riscv: Add cycle & instret privilege mode filtering support

target/riscv/cpu.c        |   2 +
target/riscv/cpu.h        |  17 +++
target/riscv/cpu_bits.h   |  34 ++++++
target/riscv/cpu_cfg.h    |   1 +
target/riscv/cpu_helper.c |  17 ++-
target/riscv/csr.c        | 251 ++++++++++++++++++++++++++++++--------
target/riscv/pmu.c        |  64 ++++++++++
target/riscv/pmu.h        |   2 +
8 files changed, 335 insertions(+), 53 deletions(-)

--
2.34.1