Re: [PATCH v5 2/5] target/riscv: Add cycle & instret privilege mode filtering properties

From: Atish Patra <atishp@rivosinc.com>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	Weiwei Li <liwei1518@gmail.com>,
	kaiwenxue1@gmail.com
Subject: Re: [PATCH v5 2/5] target/riscv: Add cycle & instret privilege mode filtering properties
Date: Thu, 7 Mar 2024 01:27:33 -0800	[thread overview]
Message-ID: <26ac4108-640f-41f9-884e-ed6b4e058935@rivosinc.com> (raw)
In-Reply-To: <2cff52d0-be4d-4f39-be24-cb8b4a7bb96c@linux.alibaba.com>


On 3/4/24 23:01, LIU Zhiwei wrote:
>
> On 2024/2/29 2:51, Atish Patra wrote:
>> From: Kaiwen Xue <kaiwenx@rivosinc.com>
>>
>> This adds the properties for ISA extension smcntrpmf. Patches
>> implementing it will follow.
>>
>> Signed-off-by: Atish Patra <atishp@rivosinc.com>
>> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
>> ---
>>   target/riscv/cpu.c     | 2 ++
>>   target/riscv/cpu_cfg.h | 1 +
>>   2 files changed, 3 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 1b8d001d237f..f9d3c80597fc 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -169,6 +169,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>>       ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>>       ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
>>       ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
>> +    ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
>>       ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
>>       ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
>>       ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
>> @@ -1447,6 +1448,7 @@ const char 
>> *riscv_get_misa_ext_description(uint32_t bit)
>>   const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>>       /* Defaults for standard extensions */
>>       MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
>> +    MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
>>       MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
>>       MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
>>       MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
>
> We should not add the configure option for users before the feature 
> has been implemented for bitsect reasons.
>
ok. I will move it to the patch where the feature is actually implemented.


> Thanks,
> Zhiwei
>
>> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
>> index 833bf5821708..0828841445c5 100644
>> --- a/target/riscv/cpu_cfg.h
>> +++ b/target/riscv/cpu_cfg.h
>> @@ -73,6 +73,7 @@ struct RISCVCPUConfig {
>>       bool ext_zihpm;
>>       bool ext_smstateen;
>>       bool ext_sstc;
>> +    bool ext_smcntrpmf;
>>       bool ext_svadu;
>>       bool ext_svinval;
>>       bool ext_svnapot;